An open source Xilinx Spartan 6 miniPCIe development board
1–10 of 46 posts
Re: An open source Xilinx Spartan 6 miniPCIe development board
#2Pretty cool. Does the board show up as PCIe endpoint if it's plugged into a laptop?
Re: An open source Xilinx Spartan 6 miniPCIe development board
#3Really nice design! Impressive routing, I was surprised you were able to fit two DDR chips on there as well.
It's still too bad that all the tooling for this is closed source (Altium, Xilinx ISE / Vivado, with the latter being far more offensive). But the Spartan 6 is a really nice chip otherwise.
It seems like the target application is compute acceleration. Do you have any particular applications in mind?
Re: An open source Xilinx Spartan 6 miniPCIe development board
#4So there's a serial flash on board? How many milliseconds max it takes to load the bitstream to FPGA after power on? Can you load PCIe endpoint within PCIe spec alotted time, 100 ms?
Is partial bitstream reprogramming possible?
Re: An open source Xilinx Spartan 6 miniPCIe development board
#5Pretty cool. Does the board show up as PCIe endpoint if it's plugged into a laptop?
Not on its own. You'd have to implement an endpoint on the FPGA to make it show up. (Same as most USB microcontrollers won't show up on the bus until there's appropriate code running on them.)
Re: An open source Xilinx Spartan 6 miniPCIe development board
#6Re: An open source Xilinx Spartan 6 miniPCIe development board
#7http://polysome.io/ The manufacturer. What purpose is this useful for? Can someone elaborate?
Software defined radio maybe?
Also, if you had a small motherboard with mini-pcie, this could be an interesting add on to offload processing to?
Re: An open source Xilinx Spartan 6 miniPCIe development board
#8So there's a serial flash on board? How many milliseconds max it takes to load the bitstream to FPGA after power on? Can you load PCIe endpoint within PCIe spec alotted time, 100 ms? Is partial bitstream reprogramming possible?
The FPGA is an XC6SLX100T, so the bitstream could be up to 26.7 megabits. It could take up to two seconds or so to configure the part with a large design.
Re: An open source Xilinx Spartan 6 miniPCIe development board
#9Excellent looking design. This could become a big deal for the maker community. I'm glad to see so much open source stuff coming out for hardware.
Re: An open source Xilinx Spartan 6 miniPCIe development board
#10Really nice design! Impressive routing, I was surprised you were able to fit two DDR chips on there as well. It's still too bad that all the tooling for this is closed source (Altium, Xilinx ISE / Vivado, with the latter being far more offensive). But the Spartan 6 is a really nice chip otherwise. It seems like the target application is compute acceleration. Do you have any particular applications in mind?
Another possible application: talking to high speed serial busses. This isn't just a Spartan 6, it's a Spartan 6 XCblahblahT. Usually when you see cheap Spartan 6 boards they use the non-transceiver version to cut costs without mentioning that it cuts one of the killer features of the chip! This one is the real deal. You still have to use ISE (not even Vivado; they locked the Spartan 6s out of Vivado) but it's still nice.
EDIT: they may have brought all the transceivers out to PCIe; I'd have to look closer to tell for sure.