Why Registers Are Fast and RAM Is Slow
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Why Registers Are Fast and RAM Is Slow
1–10 of 92 posts
Re: Why Registers Are Fast and RAM Is Slow
#2Cites distance and cost/power as reasons why "RAM is slow, registers are fast", not a mention of differences between SRAM and (S)DRAM.
Not worth reading.
Re: Why Registers Are Fast and RAM Is Slow
#3Theres something in between, which you will find on microcontrollers: SRAM. If you use simple architectures, like AVR, you also get completely deterministic timings for a load from SRAM (e.g. 2 cycles for AVR).
Edit: Chill, everyone. Yes, it's "implementation detail of the substrate", but it is a very important implementation detail given that it is directly exposed to the programmer as memory, not in some automagically managed cache.
Re: Why Registers Are Fast and RAM Is Slow
#4Theres something in between, which you will find on microcontrollers: SRAM. If you use simple architectures, like AVR, you also get completely deterministic timings for a load from SRAM (e.g. 2 cycles for AVR). Edit: Chill, everyone. Yes, it's "implementation detail of the substrate", but it is a very important implementation detail given that it is directly exposed to the programmer as memory, not in some automagica…
SRAM is used in every CPU, not just microcontrollers. Registers and cache are usually implemented as SRAM. The false distinction this article makes between registers and RAM is misleading and indicative of the author's general ignorance of computer architecture.
Re: Why Registers Are Fast and RAM Is Slow
#5Theres something in between, which you will find on microcontrollers: SRAM. If you use simple architectures, like AVR, you also get completely deterministic timings for a load from SRAM (e.g. 2 cycles for AVR). Edit: Chill, everyone. Yes, it's "implementation detail of the substrate", but it is a very important implementation detail given that it is directly exposed to the programmer as memory, not in some automagica…
That's the implementation detail of the substrate, TFA uses "RAM" in the sense of "main memory" which is the colloquial meaning of the acronym. Registers can be implemented in SRAM. So can CPU-level caches or various hardware buffers.
Re: Why Registers Are Fast and RAM Is Slow
#6Cites distance and cost/power as reasons why "RAM is slow, registers are fast", not a mention of differences between SRAM and (S)DRAM. Not worth reading.
Agreed. Completely misses on-die caches for instance. Article might have been accurate in the 6502 days, but not today.
Re: Why Registers Are Fast and RAM Is Slow
#7Theres something in between, which you will find on microcontrollers: SRAM. If you use simple architectures, like AVR, you also get completely deterministic timings for a load from SRAM (e.g. 2 cycles for AVR). Edit: Chill, everyone. Yes, it's "implementation detail of the substrate", but it is a very important implementation detail given that it is directly exposed to the programmer as memory, not in some automagica…
SRAM is used in every CPU, not just microcontrollers. Registers and cache are usually implemented as SRAM. The false distinction this article makes between registers and RAM is misleading and indicative of the author's general ignorance of computer architecture.
It's not misleading in the least unless you're a pedantic smartass who wants something to complain about. TFA uses terminology which "Reader Daniel Hooper" will understand, and in which RAM is a synonym for "main memory". Which is the colloquial meaning of RAM outside of hardware design labs and pedantic smartassery.
Re: Why Registers Are Fast and RAM Is Slow
#8For a way more detailed look at memory architectures and implementation, check out Ulrich Drepper's classic paper "What Every Programmer Should Know About Memory"[1]
Re: Why Registers Are Fast and RAM Is Slow
#9Great explanation for folks without a hardware background. I also enjoyed his previous article about ARM64. Thanks for sharing.
Re: Why Registers Are Fast and RAM Is Slow
#10Cites distance and cost/power as reasons why "RAM is slow, registers are fast", not a mention of differences between SRAM and (S)DRAM. Not worth reading.
Agreed. Completely misses on-die caches for instance. Article might have been accurate in the 6502 days, but not today.
> Agreed. Completely misses on-die caches for instance.
Absolutely, except for the part where he mentions them
> If you're really lucky and the value is in L1 cache, it'll only take a few cycles.