How to Write Safe Verilog: Become a PL Troll
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Re: How to Write Safe Verilog: Become a PL Troll
#2This is a fascinating glimpse into a world I know less than nothing about. I don't anticipate ever needing to code in Verilog, but I'll try to keep this in mind and look for other places where a little effort can save a lot of time.
I wonder what this has to say about type systems in general. Projects like Clojure's core.typed let you add static typing as a library where you feel like you need it, but then you don't get the benefit of statically checking everyone's code, all of the time. Perhaps a company policy on what functions need to be typed would do the trick, but at that point the compiler might as well enforce it for you.
Re: How to Write Safe Verilog: Become a PL Troll
#3"In high speed designs, it’s an error to use a signal that’s sourced from another module"
How else are you supposed to get I/O from one module to another, say a 32bit data bus? Also, what's the definition of high speed here?
"unless you like random errors"
And very hard to diagnose errors until you realize that you messed up your clock domains.
Re: How to Write Safe Verilog: Become a PL Troll
#4"In high speed designs, it’s an error to use a signal that’s sourced from another module" How else are you supposed to get I/O from one module to another, say a 32bit data bus? Also, what's the definition of high speed here? "unless you like random errors" And very hard to diagnose errors until you realize that you messed up your clock domains.
To some extent his advice suffers from the same problem that many books suffer from, in that it comes from the ASIC world while a large share of Verilog work these days is probably done to target FPGAs. For reasons too long to elaborate upon here, you can get away with a lot of things on FPGAs that may not be such a good idea on ASICs.
Re: How to Write Safe Verilog: Become a PL Troll
#5"In high speed designs, it’s an error to use a signal that’s sourced from another module" How else are you supposed to get I/O from one module to another, say a 32bit data bus? Also, what's the definition of high speed here? "unless you like random errors" And very hard to diagnose errors until you realize that you messed up your clock domains.
How else are you supposed to get I/O...
I believe the answer in this case is you latch the signal, and use a local copy. Sort of like how it is good practice to use local variables when coding.
what's the definition of high speed
Last I heard, 100MHz+
Re: How to Write Safe Verilog: Become a PL Troll
#6"In high speed designs, it’s an error to use a signal that’s sourced from another module" How else are you supposed to get I/O from one module to another, say a 32bit data bus? Also, what's the definition of high speed here? "unless you like random errors" And very hard to diagnose errors until you realize that you messed up your clock domains.
Yeah, I didn't understand that first part either. A module isn't very useful unless it's connected to other modules. I think he means something different, but I can't tell what.
Re: How to Write Safe Verilog: Become a PL Troll
#7"In high speed designs, it’s an error to use a signal that’s sourced from another module" How else are you supposed to get I/O from one module to another, say a 32bit data bus? Also, what's the definition of high speed here? "unless you like random errors" And very hard to diagnose errors until you realize that you messed up your clock domains.
To some extent his advice suffers from the same problem that many books suffer from, in that it comes from the ASIC world while a large share of Verilog work these days is probably done to target FPGAs. For reasons too long to elaborate upon here, you can get away with a lot of things on FPGAs that may not be such a good idea on ASICs.
you can get away with a lot of things on FPGAs...
Perhaps the most important thing you can get away with? Errors. Reprogramming an FPGA takes three minutes; manufacturing a new ASIC takes three months and three million dollars (or something along those lines). So dot your i's and cross your t's, baby.
Re: How to Write Safe Verilog: Become a PL Troll
#8As someone who spends 40 hours a week (and 60 - 70 lately) coding Verilog for FPGAs I'm always excited when something domain-specific hits the front page. I have no idea what a PL Troll is, though, so I think I missed the point of the entire post. Anyone care to elaborate? Google is not helpful.
Re: How to Write Safe Verilog: Become a PL Troll
#9As someone who spends 40 hours a week (and 60 - 70 lately) coding Verilog for FPGAs I'm always excited when something domain-specific hits the front page. I have no idea what a PL Troll is, though, so I think I missed the point of the entire post. Anyone care to elaborate? Google is not helpful.
Programming Languages Troll
Re: How to Write Safe Verilog: Become a PL Troll
#10"In high speed designs, it’s an error to use a signal that’s sourced from another module" How else are you supposed to get I/O from one module to another, say a 32bit data bus? Also, what's the definition of high speed here? "unless you like random errors" And very hard to diagnose errors until you realize that you messed up your clock domains.
How else are you supposed to get I/O... I believe the answer in this case is you latch the signal, and use a local copy. Sort of like how it is good practice to use local variables when coding. what's the definition of high speed Last I heard, 100MHz+
> I believe the answer in this case is you latch the signal, and use a local copy.
So the latch is local to both, and therefore not using a signal from another module?