Update on STM

#1

Post by wisesage5001 » Sun, Aug 18, 2013, 7:10 PM UTC

Update on STM
morepypy.blogspot.com

Re: Update on STM

#2

Post by kazagistar » Sun, Aug 18, 2013, 10:12 PM UTC

Is there any plans to work hardware transactional memory into the mix?

Re: Update on STM

#3

Post by kingkilr » Sun, Aug 18, 2013, 10:12 PM UTC

kazagistar wrote: post #2

Is there any plans to work hardware transactional memory into the mix?

Current HTM implementations limit the size of a transaction to the L1 cache, so for the time being, no.

Re: Update on STM

#4

Post by 4buser » Mon, Aug 19, 2013, 1:18 AM UTC

kingkilr wrote: post #3

kazagistar wrote: post #2

Is there any plans to work hardware transactional memory into the mix?

Current HTM implementations limit the size of a transaction to the L1 cache, so for the time being, no.

Even new Intel Haswell's STM?

Re: Update on STM

#5

Post by sanxiyn » Mon, Aug 19, 2013, 2:18 AM UTC

4buser wrote: post #4

kingkilr wrote: post #3

Earlier quoted context omitted.

Current HTM implementations limit the size of a transaction to the L1 cache, so for the time being, no.

Even new Intel Haswell's STM?

Yes, Intel TSX too has a limited transaction size.

Re: Update on STM

#6

Post by [deleted] » Mon, Aug 19, 2013, 4:11 AM UTC

[deleted]

Re: Update on STM

#7

Post by nn4 » Mon, Aug 19, 2013, 4:32 AM UTC

Obligatory anti STM hype links:

http://queue.acm.org/detail.cfm?id=1454466 http://webcache.googleusercontent.com/search?q=cache:HhZcU_j...

Pretty much all the generalized (not functional) memory TM schemes with adequate performance rely on hardware acceleration. If your design doesn't support that your design is wrong.