x86 architecture 1 byte opcodes
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x86 architecture 1 byte opcodes
1–10 of 35 posts
Re: x86 architecture 1 byte opcodes
#2I don't understand, without further description of the symbols.
Re: x86 architecture 1 byte opcodes
#3I don't understand, without further description of the symbols.
The explanation of the symbols is largely found here: https://www.sandpile.org/x86/opc_enc.htm
Essentially, the uppercase letter of an operand is a combination of the operand type (immediate, register, memory) along with how that is encoded (as ModR/M bytes have a register and a register/memory field), while the lowercase letter is the size of the operand (largely 8-bit/16-bit/32-bit/64-bit for the 1-byte opcodes).
Re: x86 architecture 1 byte opcodes
#4Need a couple of instructions for accessing memory (and possibly loading immediates) but otherwise seems like a perfectly adequate general-purpose instruction set. Might be fun (for some values of "fun") to write a compiler backend for it.
Re: x86 architecture 1 byte opcodes
#5Hello sizecoders ;)
Additional resources:
http://www.sizecoding.org/wiki/DOS
A nice PDF with similar content:
https://pnx.tf/files/x86_opcode_structure_and_instruction_ov...
Re: x86 architecture 1 byte opcodes
#6Need a couple of instructions for accessing memory (and possibly loading immediates) but otherwise seems like a perfectly adequate general-purpose instruction set. Might be fun (for some values of "fun") to write a compiler backend for it.
Tons of these have immediate operands. The question becomes is ADD with an implicit register destination and an immediate value in the next byte a "1-byte opcode"?
Re: x86 architecture 1 byte opcodes
#7What does the 0eh comment mean?
Re: x86 architecture 1 byte opcodes
#8What does the 0eh comment mean?
Re: x86 architecture 1 byte opcodes
#9Need a couple of instructions for accessing memory (and possibly loading immediates) but otherwise seems like a perfectly adequate general-purpose instruction set. Might be fun (for some values of "fun") to write a compiler backend for it.
Tons of these have immediate operands. The question becomes is ADD with an implicit register destination and an immediate value in the next byte a "1-byte opcode"?
Yes, indeed. I'd allow only mov to have a memory or immediate parameter as the only exception to one-byte encoding.
Re: x86 architecture 1 byte opcodes
#10I don't understand, without further description of the symbols.
Not sure why you're being downvoted. You need a to know quite a bit of esoteric knowledge to parse this beyond knowing x86 opcodes (even x86 assembly).
It's more or less the same information you get from the intel manuals (specifically appendix 2A of https://www.intel.com/content/www/us/en/developer/articles/t...). There you can also see what e.g. "Jb" means (a byte sized immediate following the instruction that specifies a sign-extended relative offset to the instruction).
One-byte opcodes here differs from 2 byte opcodes (386+ IIRC) prefixed by a 0F byte and even more convoluted stuff added later.