Show HN: Confidential computing for high-assurance RISC-V embedded systems
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Show HN: Confidential computing for high-assurance RISC-V embedded systems
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Re: Show HN: Confidential computing for high-assurance RISC-V embedded systems
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#3Re: Show HN: Confidential computing for high-assurance RISC-V embedded systems
#4How does it run on a P550 if that doesn't support CoVE?
Re: Show HN: Confidential computing for high-assurance RISC-V embedded systems
#5Can you explain what the relationship is between this and CoVE? Is ACE (this repo) the firmware, and CoVE the RISC-V hardware extensions that it requires? How does it run on a P550 if that doesn't support CoVE?
It can work on P550 because CoVE supports several "Deployment strategies", the one ACE uses is referenced in the README: CoVE spec, Appendix D, "M-mode [Trusted Security Manager] based deployment model" https://github.com/riscv-non-isa/riscv-ap-tee/blob/main/src/... -- the other appendicies detail e.g. Smmtt based designs, and apparently there's a not-yet-written "Nested Virtualization" design in Appendix C.
They also note that the P550 isn't a "true" port due to the preliminary, non-ratified H extension, and it also misses another required extension called "Sstc" but they just emulate it. (Sstc is interesting; it seems to be a performance optimization for delivering timer interrupts directly to supervisors, but I can imagine in the case of CoVE timer interrupts going through M-mode could leak data, making it more of a security issue.)
Leveraging M-mode is basically how previous security monitors like keystone worked too, back on the original HiFive Unleashed. It just sorta treats M-mode as an analogue to the "secure world" in ARM parlance, though there is no requirement that M-mode has e.g. an encrypted memory controller and dedicated memory region, and I'm guessing other things (I'm not super familiar with TrustZone.)
Broadly speaking this reminds me as a kind of a evolution/combination of Microsoft's Komodo (formally verified, but was only for e.g. SGX-style enclaves) and existing M-mode TEE systems like Keystone -- but upgraded to support "Confidental Computing" virtual machines. So that's quite nice.
Re: Show HN: Confidential computing for high-assurance RISC-V embedded systems
#6Re: Show HN: Confidential computing for high-assurance RISC-V embedded systems
#7Re: Show HN: Confidential computing for high-assurance RISC-V embedded systems
#8I'm interested to know the safe definition of 'limited' connectivity - is there some kind of boundary which logical reasoning can't support?
Re: Show HN: Confidential computing for high-assurance RISC-V embedded systems
#9How does this differ from Keystone?
(1) ACE leverages hardware virtualization support, including an MMU, to enable confidential virtual machines. In contrast, Keystone is designed for simpler processors that rely on just machine/supervisor/user privilege levels and physical memory protection (PMP), making it more suitable for process-based enclaves—similar to architectures like Komodo or Intel SGX. In that sense, ACE is conceptually closer to Intel TDX, but tailored for a different domain: embedded systems rather than cloud infrastructure.
(2) In ACE, the architecture and code are simplified to facilitate formal verification.
Re: Show HN: Confidential computing for high-assurance RISC-V embedded systems
#10Can you explain what the relationship is between this and CoVE? Is ACE (this repo) the firmware, and CoVE the RISC-V hardware extensions that it requires? How does it run on a P550 if that doesn't support CoVE?
Ultimately, we should expect multiple CoVE implementations optimized for different domains. For instance, in cloud environments, the focus is on maximizing performance and resource utilization—typically requiring full CoVE support and advanced hardware features such as Smmtt and AIA. Salus from Rivos is an example of such a high-end implementation. In contrast, embedded systems have limited power and silicon budgets, and thus prioritize simpler hardware. These systems trade off performance and accept memory fragmentation in favor of reduced hardware complexity and cost—ACE is designed with this trade-off in mind.
ACE runs on P550 by emulating the missing hardware features. This enables experimental deployment on real hardware. (P550 is the first commercially available RISC-V processor with virtualization support.)