AMD's Turin: 5th Gen EPYC Launched
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AMD's Turin: 5th Gen EPYC Launched
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Re: AMD's Turin: 5th Gen EPYC Launched
#2> Apparently we now think 64 cores is ‘lower core count’. What a world we live in.
64 cores is a high-end gaming rig. Civilization VII won't run smoothly on less than 16.
Re: AMD's Turin: 5th Gen EPYC Launched
#3> Apparently we now think 64 cores is ‘lower core count’. What a world we live in. 64 cores is a high-end gaming rig. Civilization VII won't run smoothly on less than 16.
Civilization VII won't run smoothly.
Only recently I managed to build a PC that will run Civ 6 smoothly during late game on huge map
Re: AMD's Turin: 5th Gen EPYC Launched
#4> Apparently we now think 64 cores is ‘lower core count’. What a world we live in. 64 cores is a high-end gaming rig. Civilization VII won't run smoothly on less than 16.
Civilization VII won't run smoothly. Only recently I managed to build a PC that will run Civ 6 smoothly during late game on huge map
What are the specs?
Tangentially related, but I need to go check a18 civ 6benchmarks. The experience on my a15 with small map sizes was surprisingly good.
Re: AMD's Turin: 5th Gen EPYC Launched
#5ChipsAndCheese is one of the few new tech publications that really knows what they are talking about, especially with these deep dive benchmarks.
With the loss of Anandtech, TechReport, HardCOP and other old technical sites, I'm glad to see a new publisher who can keep up with the older style stuff.
Re: AMD's Turin: 5th Gen EPYC Launched
#6The part with only 16 cores but 512MB L3 cache ... that must be for some specific workload.
Re: AMD's Turin: 5th Gen EPYC Launched
#7> Apparently we now think 64 cores is ‘lower core count’. What a world we live in. 64 cores is a high-end gaming rig. Civilization VII won't run smoothly on less than 16.
Civ 6 really doesn't utilize cores as much as one would think. I mean it'll spread the load across a lot of threads, sure, but it never seems to actually... use them much? E.g. I just ran the Gathering Storm expansion AI benchmark (late game map completely full of civs and units - basically worst case for CPU requirements and best case for eating up the multicore performance) on a 7950X 16 core CPU and it rarely peaked over 30% utilization, often averaging ~25%. 30% utilization means a 6 core part (barring frequency/cache differences) should be able to eat that at 80% load.
https://i.imgur.com/YlJFu4s.png
Whether the bottleneck is memory bandwidth (2x6000 MHz), unoptimized locking, small batch sizes, or something else it doesn't seem to be related to core count. It's also not waiting on the GPU much here, the 4090 is seeing even less utilization than the CPU. Hopefully utilization actually scales better with 7, not just splits up a lot.
Re: AMD's Turin: 5th Gen EPYC Launched
#8The part with only 16 cores but 512MB L3 cache ... that must be for some specific workload.
Does anyone know if modern AMD chips allow mapping the L3 cache and using it as TCM instead of cache? I know older non-X86 processors supported this (and often booted into that mode so that the memory controllers could be brought up), but not sure if it's possible today. If so, that would sure make for some interesting embedded use cases for a large DRAM-less system...
Re: AMD's Turin: 5th Gen EPYC Launched
#9The part with only 16 cores but 512MB L3 cache ... that must be for some specific workload.
Oracle can charge $40-$100k+ for EE including options per core (times .5)...and some workloads are very cache sensitive. So a high cache, high bandwidth, high frequency, high memory capacity 16 core CPU[1] (x2 socket) might be the best bang for their buck for that million dollar+ license.
[1] https://www.amd.com/en/products/processors/server/epyc/9005-...
Re: AMD's Turin: 5th Gen EPYC Launched
#10> Apparently we now think 64 cores is ‘lower core count’. What a world we live in. 64 cores is a high-end gaming rig. Civilization VII won't run smoothly on less than 16.
I can't help but think that this sounds more like a failure to optimize at the software level rather than a reasonable hardware limitation.