Intel CPU Die Topology
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Intel CPU Die Topology
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Re: Intel CPU Die Topology
#2Re: Intel CPU Die Topology
#3Re: Intel CPU Die Topology
#4Why is the rtt measured here on canon lake so asymmetric? I would have expected symmetry along the leading diagonal.
Re: Intel CPU Die Topology
#5Why is the rtt measured here on canon lake so asymmetric? I would have expected symmetry along the leading diagonal.
And why is core 0 magical on that machine?
Re: Intel CPU Die Topology
#6Earlier quoted context omitted.
And why is core 0 magical on that machine?
IIRC, core 0 is the one that tends to service processor interrupts, which may mean that the data is unusually noisy in a way that tends to underestimate the RTT latency time.
Re: Intel CPU Die Topology
#7Why is the rtt measured here on canon lake so asymmetric? I would have expected symmetry along the leading diagonal.
Re: Intel CPU Die Topology
#8> Over the past 10-15 years, per-core throughput slowed down
I assume that the author meant that the acceleration of per-core throughput over time has slowed down, not the throughput itself.
Re: Intel CPU Die Topology
#9Earlier quoted context omitted.
IIRC, core 0 is the one that tends to service processor interrupts, which may mean that the data is unusually noisy in a way that tends to underestimate the RTT latency time.
There’s a similar weird artifact at index 64.
Re: Intel CPU Die Topology
#10throughput of what?