RISC-V assembly patch for FFmpeg by SiFive
1–6 of 6 posts
Re: RISC-V assembly patch for FFmpeg by SiFive
#2Why did they use `vslidedown v1, v2, 1` instead of `vslide1down v1, v2, x0`?
Re: RISC-V assembly patch for FFmpeg by SiFive
#3Why did they use `vslidedown v1, v2, 1` instead of `vslide1down v1, v2, x0`?
Heh. The use of `vslidedown` was also what drew my eyes. But in my case the thoughts were "that's supposed to be a pretty slow instruction, included mostly for debuggers to use".
I wonder if they've run it on any actual RVV 1.0 hardware. I guess probably in an FPGA.
Tempted to convert that to RVV 0.7.1 and submit it...
Re: RISC-V assembly patch for FFmpeg by SiFive
#4Why did they use `vslidedown v1, v2, 1` instead of `vslide1down v1, v2, x0`?
Heh. The use of `vslidedown` was also what drew my eyes. But in my case the thoughts were "that's supposed to be a pretty slow instruction, included mostly for debuggers to use". I wonder if they've run it on any actual RVV 1.0 hardware. I guess probably in an FPGA. Tempted to convert that to RVV 0.7.1 and submit it...
> Tempted to convert that to RVV 0.7.1 and submit it
Have you seen https://arxiv.org/abs/2304.10324 yet?
Here is their script: https://github.com/RISCVtestbed/rvv-rollback
Re: RISC-V assembly patch for FFmpeg by SiFive
#5Why did they use `vslidedown v1, v2, 1` instead of `vslide1down v1, v2, x0`?
Heh. The use of `vslidedown` was also what drew my eyes. But in my case the thoughts were "that's supposed to be a pretty slow instruction, included mostly for debuggers to use". I wonder if they've run it on any actual RVV 1.0 hardware. I guess probably in an FPGA. Tempted to convert that to RVV 0.7.1 and submit it...
My thought was that `vslidedown` with an immediate 1 technically does less work than slide1down, and maybe they special cases that one in hardware, but that seems quite unlikely.
Edit: actually idk if there is a version of `vslidedown` that is allowed to set the values to an undefined state.
Re: RISC-V assembly patch for FFmpeg by SiFive
#6Earlier quoted context omitted.
Heh. The use of `vslidedown` was also what drew my eyes. But in my case the thoughts were "that's supposed to be a pretty slow instruction, included mostly for debuggers to use". I wonder if they've run it on any actual RVV 1.0 hardware. I guess probably in an FPGA. Tempted to convert that to RVV 0.7.1 and submit it...
> Tempted to convert that to RVV 0.7.1 and submit it Have you seen https://arxiv.org/abs/2304.10324 yet? Here is their script: https://github.com/RISCVtestbed/rvv-rollback
Yup, I've seen that, and I've been in communication with Joseph and Maurice about one or two things recently.