The RISC Deprogrammer

The article does clear up a few things. Could have been a little less acerbic though.

The author seems to have been quite wound up by claims that "my high end desktop / server (insert ARM / RISC-V to taste) is better than your x86 because 'RISC'".

Fair enough. It's an 80's debate really. ISA is probably by a long margin not the most important factor in these comparisons.

But he says it makes no difference at all without evidence.

And he ignores that there is a whole world of simpler (especially in-order) cores where ISA probably does matter a lot.

"In contrast, 16-bit processors could only address 64-kilobytes of memory, and weren't really practical for real computing."

?

It kind of pushed their own definition of what RISC is. They also confuse the definition of what a 16-bit computer is and ignore the many commercial successes in 16-bit minicomputers such as the Nova. It is clever to point out that the most useful definition of RISC is that it’s a tradeoff.

The point remains that a simplified ISA that’s easy to decode (and, more recently) implement dynamic reordering, will always have an edge by freeing up resources that can be dedicated to execution of the workload rather than housekeeping (as in resolving all inter-instruction dependencies).

OTOH, going too far in that direction gives you VLIW, which has proven itself to be a pain more often than not.

So, this is interesting so far and I'm bookmarking it for the depth of the author's historical knowledge, but saying "horizontal microcode" was the main difference that "no one talks about"...I mean I was told this was the very difference that make RISC distinct from x86 and friends (what I see now were VAX-like archs), the simpler transistor logic without the crazy micro-programs and the pipelining, I thought this was common knowledge. Is there some other context people think of when they talk about RISC that I'm unaware of?