Why I’m not excited about RISC-V
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Why I’m not excited about RISC-V
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Re: Why I’m not excited about RISC-V
#2> on a higher level RISC-V has three problems: fragmentation, fragmentation and fragmentation.
So... basically the same issues we deal with on ARM.
I sympathize with the people who are reminiscent of relatively bog-standard x86 chips. But Apple said this isn't the future, and we're not allowed to second-guess them. The best we can do is make an FOSS architecture and hope they don't... Oh God Damn It[0]
[0] https://riscv.org/news/2021/09/apple-exploring-risc-v-hiring...
Re: Why I’m not excited about RISC-V
#3>fragmentation
Lowest effort FUD. Bah.
Re: Why I’m not excited about RISC-V
#4but who remembers Beagle Board nowadays?
Lots of us. The Beagle Board is a development/evaluation board, a springboard into using the TI Sitara in finished production designs that don't need Beagle Boards. This is what TI intended. This is why there is documentation, reference schematics, reference code, and errata freely available to customers. Unlike Broadcom. You're stuck with the EVK and that's all you can get.
Re: Why I’m not excited about RISC-V
#5The title “Why I’m not excited about RISC-V at the moment” would better describe the article’s content, but unfortunately, the writer didn’t pick that title.
Basically, they’re waiting for when they can buy a working CPU with stabilized vector extensions, and will pass judgment then.