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AMD's Bulldozer server benchmarks are here, and they're a catastrophe

arstechnica.com

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Re: AMD's Bulldozer server benchmarks are here, and they're a catastrophe

#2

  Again, one can't help but feel that a hypothetical 16-core
  Magny-Cours would have been a better option.
I think that this quote demonstrates exactly the reason that AMD went forward with their catastrophe - current architectures can't get much more parallel. AMD is betting (heavily) that Intel's architecture will max out in the near future while AMD keeps improving Bulldozer. Should be interesting.

Re: AMD's Bulldozer server benchmarks are here, and they're a catastrophe

#3
AMD's problem is that they can't compete either in the low power high performance (the 45w and under laptop chips), or high power high performance markets (like the high end Xeons).

So they build massively parallel chips, and try new stuff like the Bulldozer platform, which creates a bunch of trade offs. It's very similar in concept to the Sun/Oracle Sparc T-series, with lots of great performing integer cores, and (at least on the first models) less than stellar floating point.

The best thing they ever did was to acquire ATI, which gave them great integrated graphics and allowed fairly balanced and inexpensive platforms. Their long term problem is that the really lucrative parts of the business are all being taken by Intel.

Re: AMD's Bulldozer server benchmarks are here, and they're a catastrophe

#4
post #2

Again, one can't help but feel that a hypothetical 16-core Magny-Cours would have been a better option. I think that this quote demonstrates exactly the reason that AMD went forward with their catastrophe - current architectures can't get much more parallel. AMD is betting (heavily) that Intel's architecture will max out in the near future while AMD keeps improving Bulldozer. Should be interesting.

I don't see evidence of this. Intel has moved to a more scalable ring bus while AMD is still using a crossbar (although the Bulldozer module design should allow each pair of cores to share a crossbar port).

Re: AMD's Bulldozer server benchmarks are here, and they're a catastrophe

#5
post #4
post #2

Again, one can't help but feel that a hypothetical 16-core Magny-Cours would have been a better option. I think that this quote demonstrates exactly the reason that AMD went forward with their catastrophe - current architectures can't get much more parallel. AMD is betting (heavily) that Intel's architecture will max out in the near future while AMD keeps improving Bulldozer. Should be interesting.

I don't see evidence of this. Intel has moved to a more scalable ring bus while AMD is still using a crossbar (although the Bulldozer module design should allow each pair of cores to share a crossbar port).

The HyperTransport (HT) crossbar offered more options, although people didn't tend to use it like that. I can only think of a handful of examples (the Sun X4500/X4540 for example) that took full advantage of the expanded I/O functionality it offered, and there were even a few FPGA solutions that could have been used to create really innovative custom logic designs.

The problem was that, outside of totally custom solutions like the above, it didn't offer enough of a benefit to AMD, especially once Intel jumped on the memory directly attached to CPU bandwagon.

Re: AMD's Bulldozer server benchmarks are here, and they're a catastrophe

#6
This doesn't exactly come as a surprise. It was already obvious from the desktop parts that something had gone horribly wrong. There just weren't any bright spots there.

Worse single-threaded performance despite much larger cores (even counting each "module" as two "cores" rather than two "threads"). No improvement in clock speeds despite a newer design an deeper pipelines. No improvement in multi-threaded workloads core-for-core. And it seems hard to give credit for the improved multi-threaded performance per-socket, given the huge increase in both transistor count and die size.

It would really be interesting to know what actually went wrong. The new process? The rumored switch to automated design methodology? Unfortunately the answer to the question posed by the article seems obvious... They had to persevere with this and ship it, since they didn't have the resources for a plan B.

Re: AMD's Bulldozer server benchmarks are here, and they're a catastrophe

#9
This article is impressively bad.

While the 8-module chip does share a few things (mainly a vector processing unit, that becomes two when doing the 128-bit SSE operations) they really can run 16 threads on 16 ALUs. But, they'll have sse contention if they schedule more than 8 256-bit vector operations (sadly intel won't bring this instruction set to market for a bit). Bulldozer is pretty cool, but sadly the tech press decides to shit on the underdog in a market that multiple companies have successfully sued the monopolist for anti-competitive behavior. :(

Re: AMD's Bulldozer server benchmarks are here, and they're a catastrophe

#10
post #9

This article is impressively bad. While the 8-module chip does share a few things (mainly a vector processing unit, that becomes two when doing the 128-bit SSE operations) they really can run 16 threads on 16 ALUs. But, they'll have sse contention if they schedule more than 8 256-bit vector operations (sadly intel won't bring this instruction set to market for a bit). Bulldozer is pretty cool, but sadly the tech pres…

While the 8-module chip does share a few things (mainly a vector processing unit

And more importantly, the decode and dispatch unit, which only run every other clock for a given core -- thus limiting any given core to a theoretical maximum of a mere 2 IPC, and in practice a lot more than that since the dispatch unit has limitations of its own, nevermind branch mispredictions and such.

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