RISC-V J extension – Instructions for JITs
1–10 of 56 posts
Re: RISC-V J extension – Instructions for JITs
#2Nice to see Wasm popping up in proposals like this one :)
Re: RISC-V J extension – Instructions for JITs
#3For tagged values, I loved the POWER rlwinm: Rotate Left Word Immediate aNd with Mask (and it's companion rlimi). Pretty much any sane tagging scheme could be converted to the unboxed value with that single instruction; even somewhat exotic tagging schemes like mixing high-bit and low-bit tagging could be handled by it.
Of course in modern architectures being able to do something in one instruction is only tenuously related to being able to do something quickly, but it was a super handy instruction back in the day.
Re: RISC-V J extension – Instructions for JITs
#4It's worth noting that on systems with real cache coherency (MOESI for example) where for example writing data into the dcache to an address A results in cache line shootdown in the icache as part of fetching an 'exclusive/modified' line into the dcache - in this world EXPORT.I is essentially a no-op because what it requires the icache implement (shootdown of icache lines) has already happened naturally.
Equally on such a system the only thing left for FENCE.I to do is to flush any (potentially now bogus) subsequent instructions that are in the execution pipe that might have been prefetched before the writes occurred. In such a system FENCE.I and IMPORT.I are identical.
Hopefully the people writing this spec are listening ... please make sure your spec understands high end systems like this and doesn't add stuff that require special cases in systems that do ubiquitous coherency right
Re: RISC-V J extension – Instructions for JITs
#5I suspect it won't be long before RISC-V becomes not-so-RISC. Even ARM added FJCVTZS.
Re: RISC-V J extension – Instructions for JITs
#6For tagged values, I loved the POWER rlwinm: Rotate Left Word Immediate aNd with Mask (and it's companion rlimi). Pretty much any sane tagging scheme could be converted to the unboxed value with that single instruction; even somewhat exotic tagging schemes like mixing high-bit and low-bit tagging could be handled by it. Of course in modern architectures being able to do something in one instruction is only tenuously…
I heard someone use those instructions once as examples of something compilers could do better than humans writing assembly -- Apple's MPW C compilers for PowerPC were capable of peephole optimizations that would produce them where a human might not think of them. (At least, that was the argument.)
Re: RISC-V J extension – Instructions for JITs
#7I suspect it won't be long before RISC-V becomes not-so-RISC. Even ARM added FJCVTZS.
The fastest open source RISC-V core is already technically generating micro ops. (branch to cmov).
Re: RISC-V J extension – Instructions for JITs
#8I suspect it won't be long before RISC-V becomes not-so-RISC. Even ARM added FJCVTZS.
I think the vector operations feel very RISC. One set of operations for the different vector sizes. Another thing to remember is that most of this stuff is an optional part of the ISA.
A good comparison is R7RS with scheme. The vast majority of it are optional RFCs that exist for the sake consistency and aren't implemented by most schemes. The "mandatory" parts are specified via R7RS-small and work is being done on R7RS-large, though even that won't contain every RFC.
I could see us ending up with an equivalent for RISC-V where a common group of extensions get grouped together as a standard (likely including stuff like virtualization support but excluding vector operations).
Re: RISC-V J extension – Instructions for JITs
#9For tagged values, I loved the POWER rlwinm: Rotate Left Word Immediate aNd with Mask (and it's companion rlimi). Pretty much any sane tagging scheme could be converted to the unboxed value with that single instruction; even somewhat exotic tagging schemes like mixing high-bit and low-bit tagging could be handled by it. Of course in modern architectures being able to do something in one instruction is only tenuously…
I heard someone use those instructions once as examples of something compilers could do better than humans writing assembly -- Apple's MPW C compilers for PowerPC were capable of peephole optimizations that would produce them where a human might not think of them. (At least, that was the argument.)
That depends whether you mean a human who knows the instructions exist or not or a human who hasn't worked out how to use shifts to do integers mul/div by 2 yet.
Re: RISC-V J extension – Instructions for JITs
#10Wasn’t this tried with Jazelle and Java? I wonder how they will overcome the shortcomings of that attempt