Samsung Foundry Forum announcements

At what point does quantum tunnelling become a problem?

It's always been a problem to some degree. Keep in mind that 3nm is a misnomer and has no real physical meaning behind it.

I can never remember what xnm means as it varies between companies.

In this case,

Samsung's 3nm = Intel's 7nm

I am still waiting for a standard based on transistor density numbers!

First though, "5nm", "3nm" and so on are just marketing names. There is nothing about "5nm" that makes it "5nm" other than the company in question saying it is. Some things are smaller than 5nm on a given 5nm node, and some are larger. I cannot recall exactly what node this started to be the case (there used to be an actual definition, one for DRAM, one for logic), but it was in the past two decades and got particularly ridiculous beginning around "28nm" up to now. The really concerning physical dimension for quantum tunneling to occur/not occur is "gate length," and that's been basically sitting around ~16nm (actual, real, literal 16nm), plus or minus a few nanometers (depending on the manufacturer and process in question), since about "45nm" (mid-late 2000s). So that one critical dimension isn't getting smaller. And there isn't much they can do about it right now. They are still shrinking other dimensions though, and things don't work like they used to. Powered off transistors aren't really off, and leak power. The workaround for this is that they just use bigger transistors in certain places for what's called "power gating". You get the benefits of having tons of small transistors, with a slight area penalty. In addition to power gating, they have made substantial improvements to the design of the transistors themselves. Gates now wrap around the channel on 3 sides, creating a device known as a Finfet. Silicon dioxide is no longer used as an insulator to the same extent -- hafnium dioxide preforms much better as an insulator. Gates are now metal instead of polysilicon. And there's an assortment of other changes that have occurred or are on the way. So performance has actually managed to improve somewhat, and things have still gotten smaller. The end is near... but not quite yet. Gate length is not going to budge much unless some miracle occurs, though.

There are a few comments saying that 3nm is a marketing term and that the transistors are actually larger - how is this allowed? Isn't it misleading and deceptive?