XLS: Accelerated HW Synthesis
google.github.io
XLS: Accelerated HW Synthesis
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Re: XLS: Accelerated HW Synthesis
#2Re: XLS: Accelerated HW Synthesis
#3I've been programming for 20 years and yet I have no idea what this does. Can someone ELI5?
Re: XLS: Accelerated HW Synthesis
#4I've been programming for 20 years and yet I have no idea what this does. Can someone ELI5?
Re: XLS: Accelerated HW Synthesis
#5I've been programming for 20 years and yet I have no idea what this does. Can someone ELI5?
Re: XLS: Accelerated HW Synthesis
#6I've been programming for 20 years and yet I have no idea what this does. Can someone ELI5?
Re: XLS: Accelerated HW Synthesis
#7I've been programming for 20 years and yet I have no idea what this does. Can someone ELI5?
Often, such hardware is written using hardware description languages [1] like Verilog or VHDL. These languages are very low level and, in the opinion of some, a little clumsy to use.
XLS aims to provide a system for High-level synthesis [2]. The benefit of such systems is that you can more easily map interesting algorithms to hardware without being super low level.
[1] https://en.wikipedia.org/wiki/Hardware_description_language