Using SDRAM in FPGA Designs
joshbassett.info
Using SDRAM in FPGA Designs
1–10 of 26 posts
Re: Using SDRAM in FPGA Designs
#2SDRAM is cool but DDR3 is better! With LiteDRAM there is even an open source controller. LiteDRAM also works with SDRAM too.
Re: Using SDRAM in FPGA Designs
#3Thank you for releasing this! Last time I needed an SDRAM controller, I had trouble finding anything that was open source, readable, under a permissive license, and published on GitHub. I ended up using this one by Matthew Hagerty in 2014: http://codehackcreate.com/archives/444
The notes on getting the clocking right are also very much appreciated; that's always tricky with SDRAM.
Re: Using SDRAM in FPGA Designs
#4Why isn't more of the control logic inside the sdram chip/package? Even if you want to save pins it seems the interface could be much simpler.
Re: Using SDRAM in FPGA Designs
#5What compilers are people using for FPGAs? It seems all the compilers are proprietary, and not much fun to use on Linux.
Re: Using SDRAM in FPGA Designs
#6Why isn't more of the control logic inside the sdram chip/package? Even if you want to save pins it seems the interface could be much simpler.
The more-complex interface makes it possible to optimize performance with very fine adjustments - for instance, sufficiently-modern DRAM can be precharging one bank while also servicing data requests from an already precharged one. It can also help with specific data-access patterns: for instance, if the FPGA always reads a whole page then a single precharge could serve for many reads.
Re: Using SDRAM in FPGA Designs
#7What compilers are people using for FPGAs? It seems all the compilers are proprietary, and not much fun to use on Linux.
There has been significant progress in reverse engineering bitstream formats of some FPGAs which has allowed the development of open source FPGA workflows. If you want to know more, take a look at:
Icestorm http://www.clifford.at/icestorm/
Yosys http://www.clifford.at/yosys/
NextPNR https://github.com/YosysHQ/nextpnr
SymbiFlow https://symbiflow.github.io/
Re: Using SDRAM in FPGA Designs
#8This is outstanding, thanks Josh! I’ve been getting started with FPGAs and a simple dynamic memory interface with comments and discussion is a huge help.
Re: Using SDRAM in FPGA Designs
#9What compilers are people using for FPGAs? It seems all the compilers are proprietary, and not much fun to use on Linux.
At work I use Vivado. It's proprietary but I've never had any problems using it on Linux. I believe there are free editions as well. It has the same problems all FPGA tooling has (bloated, slow build times, not user friendly). Maybe some of the open source tooling improves on that, but I've never heard of anyone using it for real projects. Last I checked the open source stuff also only supported Verilog (not sure if it supports SystemVerilog too). Not the end of the world, but a lot of projects use VHDL or are mixed language.
Edit: Mostly people just use whatever software the FPGA vendor provides. So for Xilinx you use Vivado. For Intel/Altera people use Quartus. Some people do development in an IDE like Sigasi (which I've heard is much better than the vendor specific IDE's, but I've never used it), but they still build with the vendor tooling.
Re: Using SDRAM in FPGA Designs
#10Why isn't more of the control logic inside the sdram chip/package? Even if you want to save pins it seems the interface could be much simpler.
The more-complex interface makes it possible to optimize performance with very fine adjustments - for instance, sufficiently-modern DRAM can be precharging one bank while also servicing data requests from an already precharged one. It can also help with specific data-access patterns: for instance, if the FPGA always reads a whole page then a single precharge could serve for many reads.
If you want a giant ring buffer with deterministic low latency, manual refresh control is a godsend.