A Look at the AMD Zen 2 Core
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A Look at the AMD Zen 2 Core
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Re: A Look at the AMD Zen 2 Core
#2[deleted]
Re: A Look at the AMD Zen 2 Core
#3This isn't directly related to Zen 2 (sorry), but it's something I've been wondering about:
How do processors that split ops into uops implement precise interrupts? I sort of understand how the ROB is used to implement precise interrupts even with pipelining and OOO, but I don't quite see how processors map uops back to the original instruction sequence.
Re: A Look at the AMD Zen 2 Core
#4"Zen employs a dynamic predictor known as a hashed perceptron." When will Hollywood tap into this wealth of cool vocabulary?
Is this a gimmicky marketing term, or is it logical\descriptive\rational?
Re: A Look at the AMD Zen 2 Core
#5The post states:
>"Perceptrons are the simplest form of machine learning and lend themselves to somewhat easier hardware implementations compared to some of the other machine learning algorithms."
Can someone explain what is it about perceptrons that make them easier to implement in hardware?
Re: A Look at the AMD Zen 2 Core
#6The post states: >"Perceptrons are the simplest form of machine learning and lend themselves to somewhat easier hardware implementations compared to some of the other machine learning algorithms." Can someone explain what is it about perceptrons that make them easier to implement in hardware?
All you need for a perceptron is to add up all of the inputs after they’ve been multiplied by their weight. This would probably be done in parallel with a fused multiply add circuit which is fairly simple and some place to store the weights. When they change the perceptron all they need to do is record the current weights and load in the new values.
Re: A Look at the AMD Zen 2 Core
#7"Zen employs a dynamic predictor known as a hashed perceptron." When will Hollywood tap into this wealth of cool vocabulary? Is this a gimmicky marketing term, or is it logical\descriptive\rational?
https://www.wikiwand.com/en/Perceptron
Looks like an already studied technical description going back to 2005:
https://github.com/ChampSim/ChampSim/blob/master/branch/hash...
https://www.jilp.org/cbp2014/paper/DanielJimenez.pdf
> Introduced by Tarjan and Skadron 2005
> Basic idea:
> - Hash segments of branch history into different tables
> - Sum weights selected by hash functions, apply threshold to predict
> - Update the weights using perceptron learning
Re: A Look at the AMD Zen 2 Core
#8"Zen employs a dynamic predictor known as a hashed perceptron." When will Hollywood tap into this wealth of cool vocabulary? Is this a gimmicky marketing term, or is it logical\descriptive\rational?
No, it's not a marketing term. That's literally the name of the branch predictor used. See https://www.cs.utexas.edu/~lin/papers/hpca01.pdf
Re: A Look at the AMD Zen 2 Core
#9This isn't directly related to Zen 2 (sorry), but it's something I've been wondering about: How do processors that split ops into uops implement precise interrupts? I sort of understand how the ROB is used to implement precise interrupts even with pipelining and OOO, but I don't quite see how processors map uops back to the original instruction sequence.
I'm not an expert but I believe what accomplishes this task is the reorder buffer. This allows the instruction execution and its side effects to be separated.
Re: A Look at the AMD Zen 2 Core
#10"Zen employs a dynamic predictor known as a hashed perceptron." When will Hollywood tap into this wealth of cool vocabulary? Is this a gimmicky marketing term, or is it logical\descriptive\rational?
Hashed probably means that some features are mapped to a desired perceptron weight via a hash function. This serves as an implicit regularization and can be much more efficient (no need for a predetermined feature vector, sparse representation etc.). It's called hash trick in ML. Perceptron is a single layer NN. Dynamic predictor, a branch predictor that adapts to program input, not just some predetermined state (like a formula that was shown to be good enough for a collection of programs).