Hacker News Board Hacker News, browsed like a classic message board
Live data from Hacker News

Using chip memory more efficiently

news.mit.edu

Post reply on HN
Print view View original

1–10 of 15 posts

Re: Using chip memory more efficiently

#5

Post by tyfon »

I wonder if projects like openblas can make use of this. Maybe it could be baked into the cpu too somehow.

On the other hand, when reading the title I was preparing for a gory Amiga article. In this case it should be on-chip memory or is my non native english fooling me here? But it was at least in the same spirit ;)

Re: Using chip memory more efficiently

#6

Post by amelius »

I wonder how the OS is supposed to deal with this complexity. It probably needs an API for processes to reconfigure the cache. But then the cache can be private to a process or to a group of processes. Complicated stuff.

Re: Using chip memory more efficiently

#9

Post by BooneJS »

nachiketkapre wrote: post #7

FPGA BlockRAMs have been configurable for the past two decades! The CPU architecture world is borrowing some good ideas from the FPGA architects.

To be fair, BRAMs aren't reconfigurable on the fly. That is, there's no assumption of data preservation when you change them.

Processors would need to temporarily hang to reconfigure hierarchy. Execution pipelines would stop issuing and resolve all in-process instructions and push registers to a stack, the memory system would need to quiesce the memory system and flush all structures, and finally the processor could rewrite low-level addressing crossbars. Once that's done, pop the registers back into the stack and hope there's no weird interactions with any number of legacy features in any older processor architecture. :)

Post reply on HN