A small Lisp-Machine in an FPGA
aviduratas.de
A small Lisp-Machine in an FPGA
1–8 of 8 posts
Re: A small Lisp-Machine in an FPGA
#2Re: A small Lisp-Machine in an FPGA
#3Re: A small Lisp-Machine in an FPGA
#4The verilog code had been poorly written. For example, it's not common for a combinational circuit to have an input reset. Latches are inferred in some places that can cause unexpected behavior. That's just my observation though. It's cool to see projects like this. Sadly, it appears to be inactive after seeing the project log.
Re: A small Lisp-Machine in an FPGA
#5The verilog code had been poorly written. For example, it's not common for a combinational circuit to have an input reset. Latches are inferred in some places that can cause unexpected behavior. That's just my observation though. It's cool to see projects like this. Sadly, it appears to be inactive after seeing the project log.
Could you link to an example?
Re: A small Lisp-Machine in an FPGA
#6Re: A small Lisp-Machine in an FPGA
#7The verilog code had been poorly written. For example, it's not common for a combinational circuit to have an input reset. Latches are inferred in some places that can cause unexpected behavior. That's just my observation though. It's cool to see projects like this. Sadly, it appears to be inactive after seeing the project log.