HardCaml – Register Transfer Level Hardware Design in OCaml
1–4 of 4 posts
Re: HardCaml – Register Transfer Level Hardware Design in OCaml
#2Very interesting. Also not the first of its kind. BlueSpec[0] is a RTL hardware design language in Haskell.
I am confused because this, on the other hand, doesn't appear to be sponsored by a company or university. It strikes me as pretty odd that an individual could do this on his/her own.
Re: HardCaml – Register Transfer Level Hardware Design in OCaml
#3Very interesting. Also not the first of its kind. BlueSpec[0] is a RTL hardware design language in Haskell. I am confused because this, on the other hand, doesn't appear to be sponsored by a company or university. It strikes me as pretty odd that an individual could do this on his/her own. [0] http://www.bluespec.com/
It's only 28k lines of ML (wc count). Seems well within the reach of an individual.
Re: HardCaml – Register Transfer Level Hardware Design in OCaml
#4Very interesting. Also not the first of its kind. BlueSpec[0] is a RTL hardware design language in Haskell. I am confused because this, on the other hand, doesn't appear to be sponsored by a company or university. It strikes me as pretty odd that an individual could do this on his/her own. [0] http://www.bluespec.com/
Somewhat related is MyHDL, a hardware description language implemented as a Python library, that was mostly done by a single individual (Jan Decaluwe). See http://www.myhdl.org/