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TSMC 2nm Process Disclosure – How Does It Measure Up?

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Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#91

Post by phonon »

wtallis wrote: post #90
phonon wrote: post #89

Earlier quoted context omitted.

Memory = on chip cache. M4Max has loads of it....

Disabling cache as a binning strategy isn't too common these days, unless it's a cache slice associated with a CPU or GPU core that's being disabled. Large SRAMs are manufactured usually with some spare cache lines so that they can tolerate a few defects while still operating with the nominal capacity. SRAM defects are usually not the driving force behind a binning decision. Back when Intel was stagnant at 4 cores fo…

Yes...cores (CPU and GPU) have large caches. If the cache (or associated slice) is busted, so is the core.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#92

Post by hcfman »

magicalhippo wrote: post #85
hcfman wrote: post #37

Earlier quoted context omitted.

The Pi is great! Just saying, running a Pi with an object detector on batteries draws around 9W. That's big batteries and solar or wildlife use cases. But think how cool it would be if it could run on 2W. Having said that. The Jetson runs at around 7W doing that and a lot faster inference. Just a lot more expense. Likely the Jetson will eventually be something like 2nm. So maybe we see around 4W at that time running…

Jetson Nano was manufactured using the 20nm node as far as I can see[1]. Just goes to show manufacturing node isn't everything. There's a lot of various optimizations one can do depending on targets. Guess we'll just have to see what the future brings. [1]: https://en.wikipedia.org/wiki/Tegra#Tegra_X1

The latest orin modules are 4nm I'm pretty sure.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#93

Post by manquer »

UberFly wrote: post #82
loandbehold wrote: post #72

Why are American fabs built in Arizona? What's so special about AZ?

Main reasons are a stable geology and climate, access to reliable water via the salt river project that was designated for industrial use, and the historical semiconductor presence that is already in the area. The local universities also have a strong focus on tech.

Taiwan is a humid island on the ring of fire , is any of the environmental factors actually all that important?

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#94

Post by Dylan16807 »

adgjlsfhk1 wrote: post #22
ramshanker wrote: post #15

How much would the Non-Recurrent Cost associated with designing a RISC-V CPU using this 2nm? EDA Tools, Photo-Masks, One Time Chip Design Engineer Cost, Simulation/Virtual Verification and so on. I mean every thing till tape-out.

Riscv doesn't need smaller nm. It just needs someone to actually design and release a good core design. 14nm (or 4 or anything in between) is perfectly suffient to make a Riscv chip 10x faster than any Riscv that currently exist.

x86 and Arm don't "need" smaller nm either, but there is always a market in speeding up general purpose CPUs.

10x is cool but when that's still catching up it's not done.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#95

Post by Dylan16807 »

zozbot234 wrote: post #53
distances wrote: post #50

Earlier quoted context omitted.

The article linked in another comment pointed out that cost per transistor keeps falling, and it's just the fast increasing fixed costs that make it seem otherwise. https://semianalysis.com/2022/07/24/the-dark-side-of-the-sem...

Right, but the "fast increasing fixed costs" are what really matters usually. It's not just perception.

It depends on how big of a run you want to do.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#96

Post by SpecialistK »

manquer wrote: post #93
UberFly wrote: post #82

Earlier quoted context omitted.

Main reasons are a stable geology and climate, access to reliable water via the salt river project that was designated for industrial use, and the historical semiconductor presence that is already in the area. The local universities also have a strong focus on tech.

Taiwan is a humid island on the ring of fire , is any of the environmental factors actually all that important?

You can't choose where you're from, but you can choose where you go afterwards.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#97

Post by mort96 »

Dylan16807 wrote: post #94
adgjlsfhk1 wrote: post #22

Earlier quoted context omitted.

Riscv doesn't need smaller nm. It just needs someone to actually design and release a good core design. 14nm (or 4 or anything in between) is perfectly suffient to make a Riscv chip 10x faster than any Riscv that currently exist.

x86 and Arm don't "need" smaller nm either, but there is always a market in speeding up general purpose CPUs. 10x is cool but when that's still catching up it's not done .

There are already companies making huge, expensive, high-performance chips for x86 and ARM; chips which are operating at the limit of what's physically possible. There aren't chips which do that for RISC-V to my knowledge.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#98

Post by mort96 »

bigtimesink wrote: post #86
josaka wrote: post #73

Earlier quoted context omitted.

I suspect it's, in part, because humidity is low. The fab needs to tightly control humidity and temperature. Pulling water from air is energy intensive. Facilities team in the fab I used to work in said their most energy intensive days where the most humid days.

Humidity in Taiwan can be very high.

And I'm betting that combatting that humidity is a significant cost for TSMC.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#99

Post by Dylan16807 »

mort96 wrote: post #97
Dylan16807 wrote: post #94

Earlier quoted context omitted.

x86 and Arm don't "need" smaller nm either, but there is always a market in speeding up general purpose CPUs. 10x is cool but when that's still catching up it's not done .

There are already companies making huge, expensive, high-performance chips for x86 and ARM; chips which are operating at the limit of what's physically possible. There aren't chips which do that for RISC-V to my knowledge.

I don't see how that changes things. The end goal is the same. x86 and Arm are much further along, but that doesn't mean they "need" better lithography any more or less than RISC-V "needs" it.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#100

Post by manquer »

SpecialistK wrote: post #96
manquer wrote: post #93

Earlier quoted context omitted.

Taiwan is a humid island on the ring of fire , is any of the environmental factors actually all that important?

You can't choose where you're from, but you can choose where you go afterwards.

Arizona seems a particularly bad place to choose freely.

Fabs consume enormous quantities of water and Arizona (and the sw) are already in precarious position, and not even a semi viable theoretical option like desalination possible in the future

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