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AMD's Turin: 5th Gen EPYC Launched

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Re: AMD's Turin: 5th Gen EPYC Launched

#91
post #34

Earlier quoted context omitted.

Naples, Rome, Milan, Genoa, and Turin are just cities in Italy; I'm not sure what's childish about that. They have to use something for codenames.

Whats wrong with an arbitary 16 digit number?

They're hard to understand and memorize.

The marketing departments of monitor manufacturers still haven't figured this one out yet.

Re: AMD's Turin: 5th Gen EPYC Launched

#92
post #77

The weirdest one of the bunch is the AMD EPYC 9175F: 16 cores with 512MB of L3 cache! Presumably this is for customers trying to minimize software costs that are based on "per-core" licensing. It really doesn't make much sense to have so few cores at such an expense, otherwise. Does Oracle still use this style of licensing? If so, they need to knock it off. The only other thing I can think of is some purpose like HFT…

MATLAB Parallel Server also does per-core licensing.

https://www.mathworks.com/products/matlab-parallel-server/li....

Re: AMD's Turin: 5th Gen EPYC Launched

#93
post #77

The weirdest one of the bunch is the AMD EPYC 9175F: 16 cores with 512MB of L3 cache! Presumably this is for customers trying to minimize software costs that are based on "per-core" licensing. It really doesn't make much sense to have so few cores at such an expense, otherwise. Does Oracle still use this style of licensing? If so, they need to knock it off. The only other thing I can think of is some purpose like HFT…

You can pin which cores you will use and so stay within your contract with Oracle.

Re: AMD's Turin: 5th Gen EPYC Launched

#94

Earlier quoted context omitted.

700+ threads over 2 cores, can saturate 2 400gbe Nic's 500 wats per chip (less than 2 wats per thread)... All of that in a 2U package.... 20 years ago that would have been racks of gear.

With these CPUs one can definitely hit much higher rates. 800Gbps from a single server was achieved by Netflix on much lesser systems two years ago: https://nabstreamingsummit.com/wp-content/uploads/2022/05/20... If I were to guess, this hardware can do double that, also helping that we now have actual 800Gbps Ethernet hardware. Indeed 20 years ago this would have been racks of gear at a very high cost and a huge pow…

That's one hell of a pixelflut server.

Re: AMD's Turin: 5th Gen EPYC Launched

#95
post #9

Earlier quoted context omitted.

Oracle can charge $40-$100k+ for EE including options per core (times .5)...and some workloads are very cache sensitive. So a high cache, high bandwidth, high frequency, high memory capacity 16 core CPU[1] (x2 socket) might be the best bang for their buck for that million dollar+ license. [1] https://www.amd.com/en/products/processors/server/epyc/9005-...

Surely that's a good reason for Oracle to increase their prices even more, leading to a cat-and-mouse game between CPU makers and software license sellers.

Hopefully ending when nobody uses Oracle.

Re: AMD's Turin: 5th Gen EPYC Launched

#96
post #14

Earlier quoted context omitted.

That's the usual case when vid3o g4mes are "CPU limited". One has to just look whether the game does anything high-level that other games didn't do 10 years ago. Reasonable hardware limitations related to the CPU have normally to do with complex physics effects or unusually large crowds of NPCs. (Many games are CPU limited even for fairly small crowds because their engine isn't optimized for that purpose.)

> vid3o g4mes Why do you type it like that?

Usually people do this to avoid automatic censorship systems. HN certainly has censorship in place, but I'm not aware of any that targets discussion of video games.

Re: AMD's Turin: 5th Gen EPYC Launched

#97

Here I am running a 12 year old Dell PowerEdge with dual Xeons.. I wonder when the first gen Epyc servers will be cheap fodder on eBay.

1-3rd gen Epycs can be had super cheap, but the motherboards are expensive. Also not worth getting anything less than 3rd gen unless you're primarily buying them for the pcie lanes and ram capacity - a regular current gen consumer CPU with half - a quarter of the core count will outperform them in compute while consuming significantly less power.

The reason for this is that CPU upgrades on the same board were/are very viable on SP3.

Doing that on Intel platforms just wasn't done for basically ever, it was never worth it. But upgrade to Milan from Naples or Rome is very appealing.

So SP3 CPUs are much more common used than the boards, simply because more of them were made. This is probably very bad for hobbyists, the boards are not going to get cheap until the entire platform is obsolete.

Re: AMD's Turin: 5th Gen EPYC Launched

#98
post #67
post #64

Earlier quoted context omitted.

Indeed: the first dual core server chips only launched in 2005 afaik with 90nm Denmark/Italy/Egypt Opterons and Paxville Xeons but on the Intel side it wasn't until 2007 when they were in full swing.

first dual core server chips show up generally available in 2001 with IBM POWER4, then HP PA-RISC ones in 2004, and then Opterons which was followed by "emergency" design of essentially two "sockets" on one die of of NetBurst dual core systems.

Also, I raised the question at https://retrocomputing.stackexchange.com/q/30743/3722 and one of the answers points out the 1984 Rockwell R65C29 Dual CMOS Microprocessor. It was two standard 6502 on the same die using the same bus to access the same memory... and of course IBM mainframes did it decades before.

Re: AMD's Turin: 5th Gen EPYC Launched

#99
post #36

Earlier quoted context omitted.

https://www.servethehome.com/wp-content/uploads/2024/10/AMD-... Has the full range with TDP. 500w is only for the 128/192 monster chips. The 16 core fast sku has a 320W TDP.

The 7950x3D is rated at 120w TDP. 320w seems quite high.

It is high, but it probably can sustain much higher all core frequency compared to 7950x3D (or 7950x). If nothing else, it has a bigger die and heat spreading to pull heat from, it should be easier to maintain thermal headroom on the EYPC chip.

That being said, it looks most probable what a 9175F is just a 9755 (their absolute max full size Zen5 core part) with nearly all (7/8) of their cores per CCD disabled in order to get all 512MB of cache. This means that there's a lot of extra interconnect being kept running per core which certainly would contribute to the higher TDP.

Of course, in principle this should also mean that each core (which should basically have all of a CDD's IO and cache available to it) should be screaming fast in real terms.

Of course finally, TDP is a totally fluffy number. The TDP of the 7950X3D is most probably as low as it is because of how much internal thermal resistance (the extra V-Cache layer) it has. Part of it's lower TDP isn't because "it's efficient", part of it is because "if we run it hotter, we'll melt it". The TDP for the 7950X for example is 170W.

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