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4T transistors, one giant chip (Cerebras WSE-3) [video]

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Re: 4T transistors, one giant chip (Cerebras WSE-3) [video]

#91
post #17

It has its own programming language CSL https://www.cerebras.net/blog/whats-new-in-r0.6-of-the-cereb... "CSL allows for compile time execution of code blocks that take compile-time constant objects as input, a powerful feature it inherits from Zig, on which CSL is based. CSL will be largely familiar to anyone who is comfortable with C/C++, but there are some new capabilities on top of the C-derived basics." https://g…

Due to their architecture (non-stationary dataflow) their compiler is approaching something close to a place and route FPGA algorithm

Re: 4T transistors, one giant chip (Cerebras WSE-3) [video]

#93

I wish they dug into how this monstrosity is powered. Assuming 1V and 24kW, that's 24kAmps.

Backside power delivery using through-silicon vias.

I'm sure those TSVs connect to a huge array of switching power supplies, so the 24kW doesn't travel very far at such low voltages.

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