91–100 of 105 posts
Earlier quoted context omitted.
The cores are SiFive U74-MC, the version is, I believe, 21G1. These are documented. But that design is configurable. We know B extension (optional) is enabled. I have no idea about every other setting this core can be synthesized with.
Update: B extension is apparently not actually enabled. Alas.
How well are Linux and the BSDs supported?
Not this board, but a $$ RISC-V from Xilinx's PolarFire does: - Yocto Linux BSP - Buildroot Linux BSP - Embedded Linux from Siemens Embedded - FreeBSD (coming soon) https://www.microchip.com/en-us/products/fpgas-and-plds/syst...
I've looked at the board, and don't see the appeal in price, for only mediocre CPU-parts, not enough RAM, altough good enough I/O-options. Makes no sense if you don't want to meddle with FPGAs, and just look for a fast SBC with Risc-V.
To me, at least.
Earlier quoted context omitted.
No. VisionFive2's RISC-V CPU does not have the B extension. I confirmed it on the actual device. $ cat /proc/cpuinfo processor : 0 hart : 2 isa : rv64imafdc mmu : sv39 uarch : sifive,u74-mc
As you say this, I realize I can't find anywhere that it does. I do not know why I thought it did. Possibly as U74-MC[0] supports that option. Interestingly, I also took a look at RVA22[1], and found it requires Zbb but not the whole B. Your /proc/cpuinfo isn't listing Z* extensions. Maybe lscpu output would be more detailed? 0. https://www.sifive.com/cores/u74-mc 1. https://github.com/riscv/riscv-profiles/blob/main/…
Earlier quoted context omitted.
As you say this, I realize I can't find anywhere that it does. I do not know why I thought it did. Possibly as U74-MC[0] supports that option. Interestingly, I also took a look at RVA22[1], and found it requires Zbb but not the whole B. Your /proc/cpuinfo isn't listing Z* extensions. Maybe lscpu output would be more detailed? 0. https://www.sifive.com/cores/u74-mc 1. https://github.com/riscv/riscv-profiles/blob/main/…
Oh, I was mistaken. I've verified that at least the rev instruction works (tested on clang -march=rv64imafdcb0p94).
Earlier quoted context omitted.
As usual. Sigh. Just Zpopcnt would go a long way.
It might have popcnt. It might have Za and Zb. It just doesn't claim to have B (the whole package).
Zba ("and-not" etc.) and Zbs (single-bit) are more obscure and less important. Zbc (carry-less multiply) is interesting.
Where is the CPU hardware manual that tells me the CPU's memory map and registers? This is why so much hardware ends up in landfills. No thanks to undocumented junk.
The CPU itself (Core Complex, including cache, irq controller, etc) is documented by SiFive: https://www.sifive.com/cores/u74-mc Unfortunately there appears to be no detailed documentation at all (unless you count a pile of Linux and bootloader patches, which I don't) for the peripherals, etc, outside of the core complex on the SoC: https://doc-en.rvspace.org/Doc_Center/jh7110.html
This is what drives me crazy. Vendor claims "open source" which means an outdated linux image and the source code is wrapped up inside of a megalith build monstrosity like penguintronix or yocto. Utter junk these things are.
Earlier quoted context omitted.
> 1 Processor, 1 Core, 4 Threads Any idea why StarFive went with this choice for an SBC? I remember POWER7 also having 4 SMT, but it felt right for a superscalar multi-core CPU.
Embarrassingly I thought I had a Quad-Core based on `lscpu`. I have been meaning to make use of it but so far just as a vnc server which works well loading XFCE on the minimal desktop image. Edit: can see below that it is indeed a quad core... Embarrassed I took an internet strangers off the cuff remark as gospel
Quad-core 64-bit RISC-V SiFive U74 (RV64GC) processor @ up to 1.5 GHz with 32KB D-Cache, 32KB I-cache
Single-core 64-bit RISC-V SiFive S7 (RV64IMAC) monitor core with 16KB I-cache, 8KB DTIM
Single-core 32-bit RISC-V SiFive E24 (RV32IMFC) real-time control core with 16KB I-cache