They already have ROCm, just that it lacks Windows compatibility.
Thanks! I was hoping somebody would steer me in the right direction if they had something. I wonder when AMD will focus on making things that are developer focused, I know for example that Intel has their own C++ compiler, not sure if AMD has one, though I heard it mentioned they've been contributing to LLVM. If the tooling developers use is enhanced for your hardware platform it will make it almost a no brainer to u…
currently the PCIe card would need some kind of driver to be written on the OS to communicate with it. There's SoC devices that have a soft processor on it that runs a linux kernel and can communicate with the FPGA.
Are many of those devices actually reprogramming the FPGA at runtime from the OS running on the soft processor, though? My impression was that you tended to define pretty static blocks of functionality (you know, hash calculators for your bitcoin mining or whatever), and then just communicate to those from the OS using interrupts and a shared memory interface like any other peripheral.
On the Zynq family of devices, you can load bitstreams at runtime from Linux through a device file in /dev
It's quite an interesting world where AMD has one of the 8 cores on a chip-let be a Xilinx FPGA. The only issue is they are not easy enough to program but maybe AMD can get out ahead of Nvidia on this one and define the software stack here in the way Nvidia did with CUDA.
VHDL / Verilog is very different, but not necessarily harder per-se. It's just people spend 4 years learning "normal" programming, and at best have a one-semester course which uses VHDL. But yes, a software stack would help.
As an FPGA dev, I tend to think of HDLs akin to HTML than “code”. It’s just a DSL to describe a graph. Actually pretty similar to how tensorflow is designed.
I have been looking forward to this happening for a long time. A quick search on my past comment shows that was 2016. And I remember checking Xilinx market cap last year and it was ~$30+ B, while AMD was only ~$50 B. I was thinking the chance of that ever happening is going to be very slim. ( I was an AMD Shareholder, but I never thought it would be $100B mark cap company, sold it all last year) Now AMD is at $100B+,…
back in 2015, Dell bought EMC and Vmware. both combined had a way bjgger market cap than Dell. yet, Dell bought them by raising money from the market
I'm surprised with that move of AMD, there is nothing special in Xilinx except their 'super protected' compilers. Dunno why people think that there is some sophisticated magic inside FPGA chips.
GHz limits force companies to move more and more into parallel computing and FPGA might seem the right move, but it is only partially a right move because for computations we don't need to simulate gates, we need arithmetic operations thus rather something like Field Programming ALU Array (FPALUA)
I'm surprised with that move of AMD, there is nothing special in Xilinx except their 'super protected' compilers. Dunno why people think that there is some sophisticated magic inside FPGA chips. GHz limits force companies to move more and more into parallel computing and FPGA might seem the right move, but it is only partially a right move because for computations we don't need to simulate gates, we need arithmetic o…
If its so trivial, why isn't there a decent competitor from all the startups? Even Altera with Intels moneybags has not managed to push past. Xilinx has a data center play, new HW with arrays of processors with local memory, RF integrated devices that are cutting edge (16x 10GSPS DACs in one chip for example). The compilers are advanced sure, but theres a lot in the silicon too...
I have been looking forward to this happening for a long time. A quick search on my past comment shows that was 2016. And I remember checking Xilinx market cap last year and it was ~$30+ B, while AMD was only ~$50 B. I was thinking the chance of that ever happening is going to be very slim. ( I was an AMD Shareholder, but I never thought it would be $100B mark cap company, sold it all last year) Now AMD is at $100B+,…
I thought Xilinx would buy AMD when AMD was at $9. How the tables have sure turned.
The best outcome for me would be more open FPGA tools, maybe even documented bitstream format This could just be a strategic acquisition for internal purposes: I bet a lot of design and architecture validation is done on big FPGAs. Maybe they wanted some custom ones?
> I bet a lot of design and architecture validation is done on big FPGAs. There was a talk at 32c3 (2015) by David Kaplan from AMD about developing and testing/verifying real world x86 CPU designs: https://media.ccc.de/v/32c3-7171-when_hardware_must_just_wor... Around minute ~11/12 he briefly mentions (among other methods) emulation on massive FPGA workstations costing something in the order of $1M.
Yep, emulation is huge. HAPS by Synoosys for example has a bunch of huge Xilinx FPGAs in there. I've never used one, but apparently it takes care of splitting the huge ASIC design over the array of FPGAs so it looks like a single chip, and can run at 100s of MHz, so way better than simulation that could be a few kHz at best
Totally agree. Being involved with FPGAs for 20+ years now, and Xilinx for the most part of it, I have witnessed the progressive decay of their software quality. The legacy Xilinx tools (Foundation) were far from perfect but at least useable -- and hackable to a degree if you needed to implement workarounds. Those were many times even suggested by Xilinx own employees that were easy to approach and responsive back in…
I just wanted to let you know that I’m going to print out a poster that says “TCL scripts (yikes, it’s 2020!)” with the Xilinx logo for our office... You can always tell when someone is a seasoned FPGA veteran by the quality of their rants about the tools.
Tcl is the de facto scripting standard for EDA (it's in thr name!), it's a quirky language, but what Xilinx has done is allow portability and compatability between it and major HW design tools. The low levels commands themselves are similar to ones ASIC designers would use, e.g. report_timing is the same as you would see in countless other EDA tools. Perhaps supporting python and TCL for scripting would be good, but not supprting TCL would have been a big mistake
I think this is a terrible idea for the future of technology. AMD would not be existentially dependent on the FPGA market and the stack is so important to cutting-edge tech that it demands focused stewardship. It's clear something needs to change in FPGA land. Xilinx and Intel both produce abhorrent FPGA software causing project delays and cancellations of cutting-edge technology dependent on their devices. Xilinx pr…
Totally agree. Being involved with FPGAs for 20+ years now, and Xilinx for the most part of it, I have witnessed the progressive decay of their software quality. The legacy Xilinx tools (Foundation) were far from perfect but at least useable -- and hackable to a degree if you needed to implement workarounds. Those were many times even suggested by Xilinx own employees that were easy to approach and responsive back in…
Vivado is amazing. TCL is chosen because its portable across almost All EDA tools, so by using it, Xilinx are ensuring your existing HW design skills apply to FPGA tools also, instead of the proprietary interfaces ISE used. So while TCL is not a language I like, it is the HW standard so it must be in any serious EDA tool. I use many EDA tools daily (design compiler, primetime, icc2, vcs, xcelium, verdi, redhawk, and vivado) all have TCL, so some scripts are portable between tools, which is I assume why Xilinx chose to also have some command compatability with the Synopsys commands. So doing this makes HW design skills portable, which I really appreciate. This was also why they moved to XDC constraints from the UCF, embraching existing standards to help engineers.