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Darpa Funds Development of New Type of Processor

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Re: Darpa Funds Development of New Type of Processor

#91

Post by white-flame »

kevinnk wrote: post #90
white-flame wrote: post #88

Earlier quoted context omitted.

That's kind of the entire point of Venray's claims: The CPUs are both plentiful and fast, and with far lower power consumption than computationally equivalent strength discrete CPU + RAM combos. They apparently only add a couple percent to the die size of the DRAMs. However, their business model presumes "Wait until a DRAM manufacturer buys us", which IMO is why nothing's moved forward. DRAM manufacture is low-margin…

The point of my post was there's not much upside that integrated DRAM/logic has that TSVs don't, but plenty of downsides. Regardless of Venray's claims, there's a reason modern high performance parallel architectures go with TSVs and interposers (Knights landing, new GPUs, some deep learning platforms, etc...) instead of logic in DRAM.

Part of that is simply silicon design inertia, though.

Do you see interposer style designs as linking up terabytes of DRAM? (at least in the near future) All the chips you're talking about are pretty major dies, not really suitable for having many stacks of them in conventionally tightly spaced DIMM arrays to reach such RAM sizes.

Of course, 3d chip advances might throw all current assumptions out the window and change the layout of everything.

Re: Darpa Funds Development of New Type of Processor

#92

Post by dnautics »

kruhft wrote: post #87
dnautics wrote: post #76

Earlier quoted context omitted.

Those do stack based computation?

They they are parallel chips with many cores (128 IIRC) with small amounts of 'stack' RAM running Forth directly. Chuck designs them 'by hand' using Color Forth, a transistor simulation model and ... Forth words. Similar to the machine found in TIS-100: http://www.zachtronics.com/tis-100/

exactly, the chips in the OP are not stack-based, are they?

Re: Darpa Funds Development of New Type of Processor

#93

Post by mackncheesiest »

roywiggins wrote: post #50
empath75 wrote: post #12

Is it just me or is the illustration of 'graphs' of totally the wrong kind of graphs? I'm sure they don't mean bar charts.

Maybe an Igon Value Problem? http://rationalwiki.org/wiki/Igon_Value_Problem

That would make sense to me.

I had to stop and chuckle when I saw the author put "[John] von Neumann architecture..." when quoting somebody who was simply talking about the industry standard term of "von Neumann architecture".

What's next? "[Alan] Turing machines"?

Re: Darpa Funds Development of New Type of Processor

#94

Post by kevinnk »

white-flame wrote: post #91
kevinnk wrote: post #90

Earlier quoted context omitted.

The point of my post was there's not much upside that integrated DRAM/logic has that TSVs don't, but plenty of downsides. Regardless of Venray's claims, there's a reason modern high performance parallel architectures go with TSVs and interposers (Knights landing, new GPUs, some deep learning platforms, etc...) instead of logic in DRAM.

Part of that is simply silicon design inertia, though. Do you see interposer style designs as linking up terabytes of DRAM? (at least in the near future) All the chips you're talking about are pretty major dies, not really suitable for having many stacks of them in conventionally tightly spaced DIMM arrays to reach such RAM sizes. Of course, 3d chip advances might throw all current assumptions out the window and chan…

> Do you see interposer style designs as linking up terabytes of DRAM?

I don't think we're going to see a terabyte of dram on an interposer for a while (4GB is about the max you can get commercially right now). I'm not sure what you're trying to get at though; even with logic in DRAM you have to go off chip to get to terabyte levels, so I don't see the advantage.

> All the chips you're talking about are pretty major dies, not really suitable for having many stacks of them in conventionally tightly spaced DIMM arrays to reach such RAM sizes.

The stacking happens in package (> Of course, 3d chip advances might throw all current assumptions out the window and change the layout of everything.

TSVs are 3D (or "2.5" depending on the configuration). You should have thrown out the assumptions back in 2014.

Re: Darpa Funds Development of New Type of Processor

#95

Post by white-flame »

kevinnk wrote: post #94
white-flame wrote: post #91

Earlier quoted context omitted.

Part of that is simply silicon design inertia, though. Do you see interposer style designs as linking up terabytes of DRAM? (at least in the near future) All the chips you're talking about are pretty major dies, not really suitable for having many stacks of them in conventionally tightly spaced DIMM arrays to reach such RAM sizes. Of course, 3d chip advances might throw all current assumptions out the window and chan…

> Do you see interposer style designs as linking up terabytes of DRAM? I don't think we're going to see a terabyte of dram on an interposer for a while (4GB is about the max you can get commercially right now). I'm not sure what you're trying to get at though; even with logic in DRAM you have to go off chip to get to terabyte levels, so I don't see the advantage. > All the chips you're talking about are pretty major…

> I'm not sure what you're trying to get at though; even with logic in DRAM you have to go off chip to get to terabyte levels, so I don't see the advantage.

Many-core processors with low-latency wide-bus on-chip random access speeds need to scale horizontally as well. Focusing on large chips means you're not going to have very many on a single motherboard, where QPI/HyperTransport/memory-bus style communication can achieve higher and more user-transparent shared memory access performance, compared to offboard communication networking.

The "stacks" I was talking about are just the rows of DIMM slots stacked together in tight proximity, compared to the number of CPUs/GPUs/etc per unit area on a multi-socket motherboard to achieve the same memory footprint. (easily apples and oranges in the current incarnations, admittedly, but focusing on end-user expandability and configuration options)

In my opinion, this type of on-chip fast-RAM model in larger memory systems would best take advantage of splitting up processing to where the memory is, as opposed to a fatter node model, especially when it comes to physical size and inter-chip communication of many chips.

However, if we soon have many-core chips with 32 parallel memory buses leading to in-package 256GB DRAM silicon, it does become more moot.

Yes, I know that 3d silicon stacking, HBM, etc exist now. While they've had some good speed & power advantages, they remain very limited in terms of memory footprint. And of course, the memory size is fixed per such a chip, and there doesn't seem to be a path for many-chip expansion solutions for anything but the top-end enterprise market. I think the Venray model has a simplicity and expandability that keeps the most advantageous tradeoffs.

Re: Darpa Funds Development of New Type of Processor

#96

Post by vvdcect »

Aron wrote: post #86
vvdcect wrote: post #62

Earlier quoted context omitted.

Maybe the money taxed from that said corporation could be channeled to pay for universal income.

Yeah, we could take the money from a corporation that is creating jobs and value right now, and use it to create incentives for people to never figure out how to be productive citizens because hey, there's no jobs.

The way things are now, that corporation is probably creating jobs in china, india or SEA and storing its "value" in Ireland. Just to sidetrack for a second, I know we're still quite far from ai taking away jobs from the software industry, but oh boy when that day comes I won't feel one bit sorry for you. It doesn't take much to fall through the cracks in society and I hope you learn this the hard way.

Re: Darpa Funds Development of New Type of Processor

#97

Post by Aron »

vvdcect wrote: post #96
Aron wrote: post #86

Earlier quoted context omitted.

Yeah, we could take the money from a corporation that is creating jobs and value right now, and use it to create incentives for people to never figure out how to be productive citizens because hey, there's no jobs.

The way things are now, that corporation is probably creating jobs in china, india or SEA and storing its "value" in Ireland. Just to sidetrack for a second, I know we're still quite far from ai taking away jobs from the software industry, but oh boy when that day comes I won't feel one bit sorry for you. It doesn't take much to fall through the cracks in society and I hope you learn this the hard way.

So you start with false hyperbole before moving onto vengeful and mean-spirited hopes for my future, all while presumably trying to capture the moral high ground because to you all problems can be solved with high taxes. I don't think you are alone and we are probably doomed. Because when your system doesn't work, people will simply double-down on the same ideas and make it worse.

Re: Darpa Funds Development of New Type of Processor

#98

Post by kevinnk »

white-flame wrote: post #95
kevinnk wrote: post #94

Earlier quoted context omitted.

> Do you see interposer style designs as linking up terabytes of DRAM? I don't think we're going to see a terabyte of dram on an interposer for a while (4GB is about the max you can get commercially right now). I'm not sure what you're trying to get at though; even with logic in DRAM you have to go off chip to get to terabyte levels, so I don't see the advantage. > All the chips you're talking about are pretty major…

> I'm not sure what you're trying to get at though; even with logic in DRAM you have to go off chip to get to terabyte levels, so I don't see the advantage. Many-core processors with low-latency wide-bus on-chip random access speeds need to scale horizontally as well. Focusing on large chips means you're not going to have very many on a single motherboard, where QPI/HyperTransport/memory-bus style communication can a…

Okay, I think we're talking past each other at this point so let me be as clear as possible: the original comparison was between TSVs and logic in DRAM. Both of these are a way to get DRAM on chip and as physically close to the core logic as possible. Logic in memory is on die, while TSVs are on package; neither can be "extended" by an end-user without connecting off chip. Neither changes the physical package size very much (TSVs are not intrinsically bigger than logic in DRAM). Both have nothing to do with off chip connections; as soon as you start talking about things happening off package they behave identically (grids of processor/DRAM combos can be done with either in exactly the same way). Any chip you like can have TSVs (many core, single core, big, small, whatever); there's​ no architecture that logic in DRAM can have that TSVs can't. Both can be used to "split up processing to where the memory is". Neither has to be a "fat node".

So with that out of the way, what exactly is the advantage of logic in memory? Because so far nothing you have described is actually an intrinsic advantage.

Re: Darpa Funds Development of New Type of Processor

#99

Post by white-flame »

kevinnk wrote: post #98
white-flame wrote: post #95

Earlier quoted context omitted.

> I'm not sure what you're trying to get at though; even with logic in DRAM you have to go off chip to get to terabyte levels, so I don't see the advantage. Many-core processors with low-latency wide-bus on-chip random access speeds need to scale horizontally as well. Focusing on large chips means you're not going to have very many on a single motherboard, where QPI/HyperTransport/memory-bus style communication can a…

Okay, I think we're talking past each other at this point so let me be as clear as possible: the original comparison was between TSVs and logic in DRAM. Both of these are a way to get DRAM on chip and as physically close to the core logic as possible. Logic in memory is on die, while TSVs are on package; neither can be "extended" by an end-user without connecting off chip. Neither changes the physical package size ve…

Right, it becomes less about individual chips' TSVs vs logic in DRAM, and more about the scalability of the architecture. In the marketplace right now, the trend for these TSV/interposer/multi-die sorts of devices is in "fat node" designs, instead of more on-board distributed designs.

Logic on DRAM should be simpler & cheaper, which would in the long tail lend itself to more horizontal scaling (and horizontal scaling is currently required to get large memory footprints economically). More elaborate & expensive designs would end up more in fat node designs. There's really no technical difference when looking at many-chip architectures as the chip package is a black box at that level, but it's more an economic one.

Re: Darpa Funds Development of New Type of Processor

#100

Post by kruhft »

dnautics wrote: post #92
kruhft wrote: post #87

Earlier quoted context omitted.

They they are parallel chips with many cores (128 IIRC) with small amounts of 'stack' RAM running Forth directly. Chuck designs them 'by hand' using Color Forth, a transistor simulation model and ... Forth words. Similar to the machine found in TIS-100: http://www.zachtronics.com/tis-100/

exactly, the chips in the OP are not stack-based, are they?

Probably.
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