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ECC and DDR5

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Re: ECC and DDR5

#81

Post by CamperBob2 »

_factor wrote: post #30
some_random wrote: post #14

Earlier quoted context omitted.

I think it's a pattern that reinforces itself, as a nanny state develops it's opinion of it's people worsens and it's more willing to use force to compel them.

Right, the opinion shifting to the people being unworthy of uncorrupted data unless they’re wealthy enough to pay the artificial extortion price for integrity.

What you're actually saying is that I shouldn't be allowed to determine what kind of RAM my application needs. Instead, you are saying that someone with a gun should dictate this choice to me.

That's what we mean when we say that people with your point of view are promoting nanny-statism. It amounts to infantilization of adult consumers and subsequent disempowerment.

Occasionally such legislation can be justified, as when genuinely hazardous products are involved, or products whose use involves wide-ranging externalities, but usually not. People can and should be educated -- and expected -- to make their own decisions about things like whether they need ECC RAM.

Re: ECC and DDR5

#82

Post by eth0up »

exmadscientist wrote: post #74
dsr_ wrote: post #50

Earlier quoted context omitted.

The primary source of uncorrelated bit-flips is, effectively, cosmic radiation. (Correlated bit-flips are likely from a manufacturing error... or, at least in one case, from excessively radioactive ceramic packaging.) The more atmosphere you have to randomly absorb high-energy photons, the better. Higher density memory drops fewer electrons in each well, which means a lower-energy photon can change the state. Corolar…

FYI, it's not so much photons (gamma rays) as muons. Muons are nasty little buggers.

If only they were as easy to detect as morons. One is easily detectable with a single glass of beer and nothing more. The other, however, needs dry ice, or a pint of beer on a slab of dry ice.

Re: ECC and DDR5

#83

Post by wmf »

willis936 wrote: post #56
dsr_ wrote: post #50

Earlier quoted context omitted.

The primary source of uncorrelated bit-flips is, effectively, cosmic radiation. (Correlated bit-flips are likely from a manufacturing error... or, at least in one case, from excessively radioactive ceramic packaging.) The more atmosphere you have to randomly absorb high-energy photons, the better. Higher density memory drops fewer electrons in each well, which means a lower-energy photon can change the state. Corolar…

>The primary source of uncorrelated bit-flips is, effectively, cosmic radiation. This gets said a lot but with little evidence. The mario speedrun bit flip has been replicated with marginal connector insertion. https://youtu.be/vj8DzA9y8ls

AFAIK it's been documented by Los Alamos since they're at high altitude.

Re: ECC and DDR5

#84

Post by adrian_b »

fvwqcecvq wrote: post #79
zargon wrote: post #36

Earlier quoted context omitted.

If you don't have ECC, you don't even know that your CPU is executing the correct code. There goes the "detectable" part.

DRAM is just one level in the memory hierarchy and it can absolutely be tested by the other levels in the system. It won't be continually monitored, and there will be a performance penalty, and it's a PITA, but it can definitely be done without hardware ECC. Even some of that can be minimized as most tests are statistical in nature anyway.

If you do not monitor it continuously, you achieve nothing, because the memory errors happen seldom and unpredictably.

Without ECC, you need a custom operating system, which will compute some error detection code, e.g. a CRC, for each read-only memory page, i.e. including all code pages and constant pages, and all cached but not dirty file system pages, and which will check the CRC codes periodically in the background.

That would still leave the read-write data segments unprotected, though on those some errors may be benign, if the locations are overwritten later without being read again.

Re: ECC and DDR5

#85

Post by tliltocatl »

dsr_ wrote: post #50
bikelang wrote: post #48

Earlier quoted context omitted.

Curious to learn more here - why would altitude play a role here? And when you say high altitude - are we talking La Paz, Bolivia (~12k feet) or Denver, CO (~5k feet)?

The primary source of uncorrelated bit-flips is, effectively, cosmic radiation. (Correlated bit-flips are likely from a manufacturing error... or, at least in one case, from excessively radioactive ceramic packaging.) The more atmosphere you have to randomly absorb high-energy photons, the better. Higher density memory drops fewer electrons in each well, which means a lower-energy photon can change the state. Corolar…

> Corolary: submarine datacenters are much better than orbital datacenters

Yea, except datacenters also need connectivity. And submarine connectivity, while not particularly expensive, is quite vulnerable - even more so than on land.

Re: ECC and DDR5

#86

Post by adrian_b »

willis936 wrote: post #76
adrian_b wrote: post #73

Earlier quoted context omitted.

There is a lot of direct evidence from increased error rates in computers on airplanes.

That's a much weaker statement than "the primary source of uncorrelated bit flips is cosmic radiation".

Cosmic radiation is always a source of errors for any kind of DRAM.

Whether it is the primary source of errors, depends on the design of the DRAM die.

In a badly designed DRAM there could be many other error causes.

The designers of a DRAM certainly attempt to minimize all the error causes that they can control. If they succeed, the cosmic radiation would remain the primary error source.

Without access to internal documents of the DRAM vendors, we cannot know if they have indeed minimized all other error causes.

In modern DRAM chips, a major error cause can also be the disturbance of some memory cells when some other cells are accessed in their neighborhood, which is the basis of the Rowhammer attacks, but which can also happen during the normal use of the memory, when certain access patterns happen by chance.

The DRAM vendors do not provide details about the behavior of their devices, with the hope that this makes harder the task for someone who wants to design a variant of the Rowhammer attacks, but this also makes impossible for the owner of the memory to predict whether an application program will not perform by chance an access pattern that will unintentionally flip some memory bits, which without ECC will not be detected and corrected.

Re: ECC and DDR5

#87

Post by metadat »

willis936 wrote: post #56
dsr_ wrote: post #50

Earlier quoted context omitted.

The primary source of uncorrelated bit-flips is, effectively, cosmic radiation. (Correlated bit-flips are likely from a manufacturing error... or, at least in one case, from excessively radioactive ceramic packaging.) The more atmosphere you have to randomly absorb high-energy photons, the better. Higher density memory drops fewer electrons in each well, which means a lower-energy photon can change the state. Corolar…

>The primary source of uncorrelated bit-flips is, effectively, cosmic radiation. This gets said a lot but with little evidence. The mario speedrun bit flip has been replicated with marginal connector insertion. https://youtu.be/vj8DzA9y8ls

Engineering computer memory to work in space is a whole field of study, see Radiation Hardened memory. The main physical difference about space is the radiation profile and radiation induced memory upset.

Are you disputing that the Earth's atmosphere absorbs and reduces the amount of ambient cosmic radiation? Or where is the skepticism coming from?

Re: ECC and DDR5

#88

Post by willis936 »

metadat wrote: post #87
willis936 wrote: post #56

Earlier quoted context omitted.

>The primary source of uncorrelated bit-flips is, effectively, cosmic radiation. This gets said a lot but with little evidence. The mario speedrun bit flip has been replicated with marginal connector insertion. https://youtu.be/vj8DzA9y8ls

Engineering computer memory to work in space is a whole field of study, see Radiation Hardened memory. The main physical difference about space is the radiation profile and radiation induced memory upset. Are you disputing that the Earth's atmosphere absorbs and reduces the amount of ambient cosmic radiation? Or where is the skepticism coming from?

I am disputing that cosmic ray showers are the obvious dominant source of terrestrial DRAM bit flips.

Re: ECC and DDR5

#89

Post by zerof1l »

nu11ptr wrote: post #51

I've always thought it odd that we don't use ECC as a standard on all computers. I think people really downplay the impact of memory issues. They can be devastating, especially over time. They will slowly corrupt your file system, documents, binary files, code, everything. You notice when things like your compressed files start giving CRC/checksum errors or your downloads don't match SHA-512. You are then left with t…

It's very important IMO that the ECC failures get reported and logged. The DDR5 on-die correction is not true ECC; the correction happens silently and is not reported or logged.

I have DDR4 ECC memory on my home server. Last week I got a crash... logged into my BMC and saw that one of the modules had "uncorrectable ECC". Then I looked over the logs and saw about 200 or so errors for the exact same module but "correctable ECC". They would happen over a short period of time followed by 4 months of no issues. Thanks to ECC and logging it was quick and easy to catch the issue right on the first occurrence, no data corruption. I have 4 modules in total, and only this one was having issues, so clearly a hardware fault.

Now imagine it was a regular non-ECC memory. There won’t be any crashes due to uncorrectable ECC; another 3 or more years would pass before corruption would become frequent enough for the issue to be noticed. At that point, there would be hundreds of corrupted files.

Re: ECC and DDR5

#90

Post by hamilyon2 »

Does encrypted memory give ECC-like detection benefit, along with rowhammer protection, for cheaper cost (only additional computation), and 100% reliable?
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