Earlier quoted context omitted.
Google is your friend.
I've looked at this several times and have never found a source that confirms what you have said. Do you have a source or not?
Narrator: There was no source.
Instruction Sets Should Be Free: The Case for RISC-V [pdf] (2014)
81–90 of 105 posts
Re: Instruction Sets Should Be Free: The Case for RISC-V [pdf] (2014)
#82Would copying an instruction set and ABI to make an interoperable processor and system be fair use in light of Google v. Oracle (2021) [0][1]? [0] https://www.supremecourt.gov/opinions/20pdf/18-956_d18f.pdf [1] https://en.wikipedia.org/wiki/Google_LLC_v._Oracle_America,_... . Edit: Changed phrasing of question. Also, to be clear I think the answer is probably yes.
You can patent an ISA. And then everyone who implements that ISA, in hardware or emulation, is infringing. Intel actually threatened lawsuits against Microsoft for implementing emulation of recent x86 instructions on ARM Windows.
Do you have a link covering that? AFAIK anything up to SSE4.2 was effectively public domain and AVX2 has recently joined that.
Re: Instruction Sets Should Be Free: The Case for RISC-V [pdf] (2014)
#83I fully support the idea of open instruction sets. I am not as much sold on the idea of cookie-cutter one-size-fits-all instruction sets. RISC-V is very nice for teaching CPU basics, and it is a great fit for tiny cores or specialized microcontrollers. Unfortunately, since it has been designed for simplicity it appears that it makes it harder building high-performance cores. RISC-V philosophy for high-performance OoO…
> More complex instructions that combine multiple processing steps would help, it seems that the core RISC-V community is opposed to that idea out of purely ideological reasons
Thats not true, the Scalar Efficiency SIG is currently working on such an extension.
See this spreadsheet of discussed instructions: https://docs.google.com/spreadsheets/u/0/d/1dQYU7QQ-SnIoXp9v... and charter: https://github.com/riscv-admin/riscv-scalar-efficiency/blob/...
Re: Instruction Sets Should Be Free: The Case for RISC-V [pdf] (2014)
#84I fully support the idea of open instruction sets. I am not as much sold on the idea of cookie-cutter one-size-fits-all instruction sets. RISC-V is very nice for teaching CPU basics, and it is a great fit for tiny cores or specialized microcontrollers. Unfortunately, since it has been designed for simplicity it appears that it makes it harder building high-performance cores. RISC-V philosophy for high-performance OoO…
> More complex instructions that combine multiple processing steps would help, it seems that the core RISC-V community is opposed to that idea out of purely ideological reasons Thats not true, the Scalar Efficiency SIG is currently working on such an extension. See this spreadsheet of discussed instructions: https://docs.google.com/spreadsheets/u/0/d/1dQYU7QQ-SnIoXp9v... and charter: https://github.com/riscv-admin/ri…
I remember last year (?) Quancomm proposing an ISA extension that brings ARM-like addressing modes and paired stores to RISC-V, and the community reaction being very negative. Happy to hear that there are now initiatives to streamline these proposals and make RISC-V a better fit for high-performance CPUs. I am looking forward to future developments!
Re: Instruction Sets Should Be Free: The Case for RISC-V [pdf] (2014)
#85Earlier quoted context omitted.
> More complex instructions that combine multiple processing steps would help, it seems that the core RISC-V community is opposed to that idea out of purely ideological reasons Thats not true, the Scalar Efficiency SIG is currently working on such an extension. See this spreadsheet of discussed instructions: https://docs.google.com/spreadsheets/u/0/d/1dQYU7QQ-SnIoXp9v... and charter: https://github.com/riscv-admin/ri…
I remember last year (?) Quancomm proposing an ISA extension that brings ARM-like addressing modes and paired stores to RISC-V, and the community reaction being very negative. Happy to hear that there are now initiatives to streamline these proposals and make RISC-V a better fit for high-performance CPUs. I am looking forward to future developments!
The negative responses were, because Qualcomm wanted to remove the C extension from the application profiles.
Qualcomm prefered a strict 32-bit instruction set, with potentially 64 bit naturally aligned instructions. RISC-V is designed for 16, 32, 48, 64 bit instructions that are 16 bit aligned, and retroactively changing that wouldn't have been a good decision. Both sides of the argument agreed that both options are resonable and don't hinder high performance designs.
Qualcomm seems to have accepted this now, as they e.g. proposes 48 bit instructions with larger immediats.
Re: Instruction Sets Should Be Free: The Case for RISC-V [pdf] (2014)
#86Re: Instruction Sets Should Be Free: The Case for RISC-V [pdf] (2014)
#87Earlier quoted context omitted.
GPT-4o retrieved this for me: https://www.macrumors.com/2023/09/06/apple-inks-new-deal-arm...
So, not a source. There's some claims in this article and in the routers article they use as source, but they're unrelated.
err...
> ... we have entered into a new long-term agreement with Apple that extends beyond 2040, continuing our longstanding relationship of collaboration with Apple and Apple’s access to the Arm architecture.
Arm's IPO F-1/A.
https://www.sec.gov/Archives/edgar/data/1973239/000119312523...
Which was linked in the MacRumors link.
Re: Instruction Sets Should Be Free: The Case for RISC-V [pdf] (2014)
#88Earlier quoted context omitted.
I wonder why this hasn't been an issue for Apple (or maybe it has?).
Apple was a co-founder of Arm [0]. "Arm was officially founded as a company in November 1990 as Advanced RISC Machines Ltd, which was a joint venture between Acorn Computers, Apple Computer (now Apple Inc.), and VLSI Technology (now NXP Semiconductors N.V)." I'm not sure of their exact licensing terms, but I'm sure as a co-founder they're favourable. [0] - https://newsroom.arm.com/blog/arm-official-history
I seem to have replied to the wrong comment. I meant to reply to the one about Intel threatening Microsoft about emulating x86 on ARM.
Re: Instruction Sets Should Be Free: The Case for RISC-V [pdf] (2014)
#89Earlier quoted context omitted.
I've looked at this several times and have never found a source that confirms what you have said. Do you have a source or not?
Narrator: There was no source.
Nah, I just don't want to baby feed people on the Internet.
https://appleinsider.com/articles/20/06/09/how-arm-has-alrea...
https://appleinsider.com/articles/08/07/30/arm_reports_finge...
Re: Instruction Sets Should Be Free: The Case for RISC-V [pdf] (2014)
#90Earlier quoted context omitted.
Narrator: There was no source.
Nah, I just don't want to baby feed people on the Internet. https://appleinsider.com/articles/20/06/09/how-arm-has-alrea... https://appleinsider.com/articles/08/07/30/arm_reports_finge...
Neither of those say what your comment implied - that they get a special deal and that’s because they are a founder.