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RISC-V SBC VisionFive 2 Officially Shipped

starfivetech.com

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Re: RISC-V SBC VisionFive 2 Officially Shipped

#81

Earlier quoted context omitted.

afaict rbpi cpu has vector instructions? if so, i wonder how much that contributes to the difference...?

a lot.

Fortunately, at least for video codecs, there's a hardware acceleration block, and it is significantly stronger than the one rpi4's SoC has.

Unfortunately, there's no drivers in the current images, and it'll take time to have proper open drivers and integration with common APIs such as vdpau.

Re: RISC-V SBC VisionFive 2 Officially Shipped

#82
post #69
post #33

Earlier quoted context omitted.

Do you have a URL for those 3.xW and 4.4W claims? For longevity 60C is better. I'm talking multiple decades at constant permanent full blast here.

https://www.design-reuse.com/news/52544/starfive-risc-v-jh71... The interesting part goes: >As for power consumption, JH7110 is separated into 8 independent power domains. CPU frequency can be configured through software. To achieve a balanced PPA, customers can set the most optimum SoC frequency based on their application scenarios and performance requirements. In sleep mode, the static power consumption of JH7110 i…

"with all the main modules under full load" does that imply GPU is 100% loaded?

I hope not, and then if I'm right and the GPU is more powerful than the Raspberry 4 one this board will run at 6W or something and then a stick-on heatsink wont do it...

Look at my link to the full copper one if I'm right:

http://www.enzotech.com/cnb_s1l.htm

I received it now and it's great (if it fits) well worth the expensive price!

Re: RISC-V SBC VisionFive 2 Officially Shipped

#83
post #82
post #69

Earlier quoted context omitted.

https://www.design-reuse.com/news/52544/starfive-risc-v-jh71... The interesting part goes: >As for power consumption, JH7110 is separated into 8 independent power domains. CPU frequency can be configured through software. To achieve a balanced PPA, customers can set the most optimum SoC frequency based on their application scenarios and performance requirements. In sleep mode, the static power consumption of JH7110 i…

"with all the main modules under full load" does that imply GPU is 100% loaded? I hope not, and then if I'm right and the GPU is more powerful than the Raspberry 4 one this board will run at 6W or something and then a stick-on heatsink wont do it... Look at my link to the full copper one if I'm right: http://www.enzotech.com/cnb_s1l.htm I received it now and it's great (if it fits) well worth the expensive price!

>does that imply GPU is 100% loaded?

What I gather from the text is that it's a calculated (from design libraries), rather than measured, full load power draw. Which would make these numbers the upper bound, and thus very good.

I might be wrong.

Either way, as these boards are reaching people, it shouldn't take long until we see measured power draw and temperatures.

Re: RISC-V SBC VisionFive 2 Officially Shipped

#84
post #40

Earlier quoted context omitted.

> It's a mess at the moment! yea, thats for sure, but i think a lot of promise too... from my cursory testing it seems gui performance is much better than hifive unmatched (window manager, apps, web browser) [edit] add geekbench https://browser.geekbench.com/v5/cpu/compare/17159543?baseli...

> 1 Processor, 1 Core, 4 Threads Any idea why StarFive went with this choice for an SBC? I remember POWER7 also having 4 SMT, but it felt right for a superscalar multi-core CPU.

Embarrassingly I thought I had a Quad-Core based on `lscpu`.

I have been meaning to make use of it but so far just as a vnc server which works well loading XFCE on the minimal desktop image.

Edit: can see below that it is indeed a quad core... Embarrassed I took an internet strangers off the cuff remark as gospel

Re: RISC-V SBC VisionFive 2 Officially Shipped

#85
post #72
post #28

How well are Linux and the BSDs supported?

Linux works somewhat, with some duct taped drivers. Freebsd boots, but that's it. Of course, as this board is the first large production run, decent spec'd and reasonably compliant This is an order of magnitude more boards than accumulated RISC-V development boards distributed to date.

Interesting. I see that NetBSD can now boot on riscv also:

https://mail-index.netbsd.org/port-riscv/

Re: RISC-V SBC VisionFive 2 Officially Shipped

#86
post #66
post #44

Earlier quoted context omitted.

The link in the GP comment is wrong - both SoCs have 4 cores, each with a single thread. The reason why this SoC is faster than HiFive Unmatched seems to be down to architectural improvements.

They both use U74, but different versions. The one in JH7110 is the 2021Q1 version, AIUI. Besides faster, it also added B extension.

No. VisionFive2's RISC-V CPU does not have the B extension. I confirmed it on the actual device.

$ cat /proc/cpuinfo processor : 0 hart : 2 isa : rv64imafdc mmu : sv39 uarch : sifive,u74-mc

Re: RISC-V SBC VisionFive 2 Officially Shipped

#88
post #85
post #72

Earlier quoted context omitted.

Linux works somewhat, with some duct taped drivers. Freebsd boots, but that's it. Of course, as this board is the first large production run, decent spec'd and reasonably compliant This is an order of magnitude more boards than accumulated RISC-V development boards distributed to date.

Interesting. I see that NetBSD can now boot on riscv also: https://mail-index.netbsd.org/port-riscv/

Good to hear. There are other interesting systems, such as xv6 (which abandoned x86 for RISC-V) or Haiku (which RISC-V support has working desktop from about a year ago, unlike aarch64 which doesn't yet).

My answer was, however, specific to systems that run on VisionFive 2.

The situation should improve dramatically once proper documentation is available.

Re: RISC-V SBC VisionFive 2 Officially Shipped

#89
post #86
post #66

Earlier quoted context omitted.

They both use U74, but different versions. The one in JH7110 is the 2021Q1 version, AIUI. Besides faster, it also added B extension.

No. VisionFive2's RISC-V CPU does not have the B extension. I confirmed it on the actual device. $ cat /proc/cpuinfo processor : 0 hart : 2 isa : rv64imafdc mmu : sv39 uarch : sifive,u74-mc

As you say this, I realize I can't find anywhere that it does.

I do not know why I thought it did. Possibly as U74-MC[0] supports that option.

Interestingly, I also took a look at RVA22[1], and found it requires Zbb but not the whole B.

Your /proc/cpuinfo isn't listing Z* extensions. Maybe lscpu output would be more detailed?

0. https://www.sifive.com/cores/u74-mc

1. https://github.com/riscv/riscv-profiles/blob/main/profiles.a...

Re: RISC-V SBC VisionFive 2 Officially Shipped

#90
post #77

Earlier quoted context omitted.

Thank you. Guessing the Z extensions are AES operations? Supervisor ops?

The cores are SiFive U74-MC, the version is, I believe, 21G1. These are documented. But that design is configurable. We know B extension (optional) is enabled. I have no idea about every other setting this core can be synthesized with.

Update: B extension is apparently not actually enabled. Alas.
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