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>This software is licensed under the MIT license Maybe consider including a MIT license in the repository. Legally, that's a bit more sane than having a line in the readme. In practice, github will recognize your license file and show the license in the indexes an d in the right column of your repository's main page.
Okay, I've added a file
In order to measure core-to-core latency, we should also learn how the cache coherence works on Intel. I am currently experimenting with microbenchmarks on Skylake microarchitecture. Due to the scalability issues with ring interconnect on CPU dies in previous models, Intel opted for 2D mesh interconnect microarchitecture in recent years. In this microarchitecture, CPU die is split into tiles each accommodating cores, caches, CHA, snoop filter etc. I want to emphasize the role of CHA here. Each CHA is responsible for managing coherence of a portion of the addresses. If a core tries to fetch a variable that is not in its L1D or L2 cache, the CHA managing the coherence of the address of the variable being fetched will be queried to learn whereabouts of the variable. If the data is on the die, the core currently owning the variable will be told to forward that variable to the requesting core. So, even though the cores that communicate with each other are physically contiguous, the location of the CHA that manages the coherence of the variable they will pass back and forth also is important due to cache coherence mechanism.
Related links:
CPU 0 1 2 3
0 0 77 77 77
1 77 0 77 77
2 77 77 0 77
3 77 77 77 0
CPU 0 1 2 3
0 0 71 71 71
1 71 0 71 71
2 71 71 0 71
3 71 71 71 0I have something similar but in C++: https://github.com/rigtorp/c2clat
I went to your homepage. Your gif "Programming in C++" made me really laugh, thanks for that! 8-) https://rigtorp.se/
I can offer the following in return: https://i.pinimg.com/736x/cc/aa/30/ccaa3008f98375c26a221c85d...
Num cores: 8
Using RDTSC to measure time: true
Num round trips per samples: 5000
Num samples: 300
Showing latency=round-trip-time/2 in nanoseconds:
0 1 2 3 4 5 6 7
0
1 70±1
2 53±1 42±0
3 73±5 134±5 80±1
4 16±0 49±1 56±1 46±1
5 63±4 28±1 128±5 67±1 66±1
6 56±1 49±1 10±0 81±4 124±4 72±1
7 57±1 57±1 45±1 10±0 63±4 130±5 87±1
Min latency: 10.1ns ±0.2 cores: (6,2)
Max latency: 134.1ns ±5.3 cores: (3,1)
Mean latency: 64.7nsThis is interesting. I'm getting much worse results on an i7-1165G7 than the ones published: Num cores: 8 Using RDTSC to measure time: true Num round trips per samples: 5000 Num samples: 300 Showing latency=round-trip-time/2 in nanoseconds: 0 1 2 3 4 5 6 7 0 1 70±1 2 53±1 42±0 3 73±5 134±5 80±1 4 16±0 49±1 56±1 46±1 5 63±4 28±1 128±5 67±1 66±1 6 56±1 49±1 10±0 81±4 124±4 72±1 7 57±1 57±1 45±1 10±0 63±4 130±5 87±1 Min…
This is interesting. I'm getting much worse results on an i7-1165G7 than the ones published: Num cores: 8 Using RDTSC to measure time: true Num round trips per samples: 5000 Num samples: 300 Showing latency=round-trip-time/2 in nanoseconds: 0 1 2 3 4 5 6 7 0 1 70±1 2 53±1 42±0 3 73±5 134±5 80±1 4 16±0 49±1 56±1 46±1 5 63±4 28±1 128±5 67±1 66±1 6 56±1 49±1 10±0 81±4 124±4 72±1 7 57±1 57±1 45±1 10±0 63±4 130±5 87±1 Min…
Might too-aggressive power saving be an issue? The spikes (100+ns) are all hyper-threads. edit: No, 4 to 6 is not a HT.
If that's the case, I think it kicks in quickly because running this with 500, 5_000 and 50_000 round trips gives results in the same ballpark.
There doesn't seem to be any difference between performance and powersave governors for this particular test.
Earlier quoted context omitted.
Rings are great for latency on low core count situations. The LCC Intel chips all have a massive 512-bit ring bus (2x256-bit in each direction) internally which delivers crazy fast core to core latency. However, this quickly starts to break down under higher core counts. Intel gets around this to some extent with its P and E cores with 4 E cores occupying the same slot on the ring bus as a P core. However, once you s…
I found that this is a very insightful overview of chip architectures today. Thank you for taking the time to spell this out! I had no idea that there were 2x2 and 1x4 chips. Do you have a link that compares those in performance?
The 3300X is consistently ahead of the 3100.
I have something similar but in C++: https://github.com/rigtorp/c2clat