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Removing characters from strings faster with AVX-512

lemire.me

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Re: Removing characters from strings faster with AVX-512

#81
post #74
post #67

Earlier quoted context omitted.

Still smells like bullshit. Let the customer decide. Who cares if it was validated? Why was it even included? Just put it behind a yes-I-really-mean-it-switch so nobody uses it by accident.

There's not many great places for such a switch, and even then, then you have to validate _that_ behavior. It's mostly just not worth it.

Several motherboard vendors added that very switch in UEFI (some even with the option to force an older microcode version AFAIK) before it was disabled in hardware by Intel

Re: Removing characters from strings faster with AVX-512

#82

Earlier quoted context omitted.

Couldn’t there be some flag on the thread that marks it as “P-core only”? Doesn’t seem hard. I don’t known Linux scheduler internals though.

Right but then you’d just have all processes with that flag all the time.

Only if glibc decides to use AVX512 for memset and such. I’m not sure if that makes sense to begin with, but it could also not do that if it detects a heterogeneous CPU.

Re: Removing characters from strings faster with AVX-512

#84

Earlier quoted context omitted.

You reschedule it only once so it doesn’t matter

I don’t see how? Once your quantum is up the thread gets put back into the scheduling pool and you have to do this all over again…

You don’t have to schedule your thread on another core at all

Re: Removing characters from strings faster with AVX-512

#85
post #77

Earlier quoted context omitted.

Actually AVX-512 predates AVX and Sandy Bridge. The original name of AVX-512 was "Larrabee New Instructions". Unlike with the other Intel instruction set extensions, the team which defined the "Larrabee New Instructions" included graphics experts hired from outside Intel, which is probably the reason why AVX-512 is a better SIMD instruction set than all the other designed by Intel. Unfortunately, Sandy Bridge (2011),…

Hmm. That's not how I recall it. The folks in Israel working on Sandybridge (Gesher), already had their AVX plans in place before LRBni was "finalized" (even by the time of "our" siggraph paper -- I was only tangentially involved, not listed -- new instructions were being added all the time). So it's more like both groups knew what the other was doing, but LRBni was free to focus primarily on graphics and a clean sla…

Indeed, as you say, the development of both LRBni and of AVX by 2 separate Intel teams stretched over many years.

Most of the development of LRBni was between 2005 and 2009, when it became publicly known. The first product with LRBni was Knights Ferry, which was introduced in 2010, being made with the older 45-nm process. Knights Ferry was used only in development systems, due to insufficient performance.

Sandy Bridge, using the newer 32-nm process, was launched in 2011. I do not know when the development of Sandy Bridge had started, but in any case the first few years of development must have overlapped with the last few years of the development of LRBni.

I suppose that there was little, if any, communication between the 2 Intel teams.

AVX was developed as an instruction set extension in the same way as the majority of the instruction set extensions had been developed by Intel since the days of Intel 8008 (1972) and until the present x86 ISA.

Intel has only very seldom introduced new instructions that had been designed having a global view of the instruction set and making a thorough analysis of which instructions should exist in order to reach either the best performance or the least programming effort.

In most cases the new instructions have been chosen so that they would need only minimal hardware changes from the previous CPU generation for their implementation, while still providing a measurable improvement in some benchmark. The most innovative additions to the Intel ISA had usually been included in the instruction sets of other CPUs many years before, but Intel has delayed to also add them as much as possible.

This strategy of Intel is indeed the best for ensuring the largest profits from making CPUs, as long as there is no strong competition.

Moreover, now the quality of the ISA matters much less for performance than earlier, because the very complex CPUs from today can perform a lot of transformations on the instruction stream, like splitting / reordering / fusion, which can remove performance bottlenecks due to poor instruction encoding.

Most programmers use only high-level languages, so only the compiler writers and those that have to write extremely optimized programs have to deal with various ugly parts of the Intel-AMD ISA.

So AVX for Sandy Bridge has been designed in the typical Intel way, having as target to be a minimal improvement over SSE.

On the other hand LRBni was designed from the ground, to be the best instruction set that they knew how to implement for performing its tasks.

So it was normal that the end results were different.

For the Intel customers, it would have been much better if Intel did not have 2 divergent developments for their future SIMD ISA, but they would have established a single, coherent, roadmap for SIMD ISA development during the next generations of Intel CPUs.

In an ideal company such a roadmap should have been established after discussions with a wide participation, from all the relevant Intel teams.

For cost reasons, it is obvious that it would not have been good for Sandy Bridge to implement the full LRBni ISA. Nevertheless, it would have been very easy to implement a LRBni subset better than AVX.

Sandy Bridge should still have implemented only 256-bit operations, and the implementation of some operations, e.g. gather and scatter, could have been delayed for a later CPU generation.

However other LRBni features, should have been present since the beginning, e.g. the mask registers, because they influence the instruction encoding formats.

The mask registers would have required very little additional hardware resources (the actual hardware registers can reuse the 8087 registers), but they would have simplified AVX programming a lot, by removing the complicated code needed to handle correctly different data sizes and alignments.

The current CPUs with AVX-512 support would have been simpler, by not having to decode 2 completely distinct binary instruction formats, for AVX and for AVX-512, which is a fact that made difficult the implementation of AVX-512 in the small cores of Alder Lake.

Re: Removing characters from strings faster with AVX-512

#86
post #60
post #55

Earlier quoted context omitted.

Weren’t those chips $10k each back then? Hardly anyone got gold Xeons.

Not even close. The blog post was 2017. Actually, I stand corrected, after double checking, Cloudflare were using Silver. Entry level data centre chips, instead of small business chips. Still not the kind of chips you'd buy for high performance infrastructure, and not intended to be used for such. Xeon Silver 4116s hit the market at $1,002.00. The Golds were $1,221.00. The performance differences are quite significan…

I’m not familiar with the model numbers. What’s the gold equivalent to the Xeon Silver 4116?

Anyway I’m sure they compared the TCO of buying more low-end chips vs fewer high-end chips.

Re: Removing characters from strings faster with AVX-512

#87
post #44

Earlier quoted context omitted.

Is it generally possible to convert rep str sequences to AVX? Could the hardware or compiler already be doing this? AVX is just the SIMD unit. I would argue the transistors were spent on SIMD, and the hitch is simply the best way to send str commands to the SIMD hardware.

Why? IIRC something like 99% of string operations are on 20 chars or less. If you're hitting bottlenecks then optimize.

If you are arguing most string ops have just a few chars and therefore don’t use vectors… why do we need to spend silicon enhancing rep prefix in the first place?

Re: Removing characters from strings faster with AVX-512

#88
post #64

Earlier quoted context omitted.

>The AVX-512 instructions were never added to the efficiency cores because it would use way too much die space and defeat the purpose of efficiency cores. Isn't the purpose of efficiency cores to be more power efficient? It's more power efficient to vectorize instructions and minimize pipeline re-ordering.

Power and area efficient. You can fit 4 E cores in the area of 1 P core. Adding AVX-512 to the E cores would significantly hamper that, though I don't know by how much.

I've been thinking about this. I think the idea of heterogeneous extensions is nuts. Intel is right to either have it on all cores or none. I think the die space would be worth it to actually have more high performance, efficient vector extensions available. Considering how many E cores are being crammed into raptor lake, I hope Intel will decide to add AVX-512 into E cores in time.
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