Mashable seems to be the new content free e-tabloid.
Breakthrough: The Secret to Making Processors 1,000 Times Faster
81–90 of 100 posts
Re: Breakthrough: The Secret to Making Processors 1,000 Times Faster
#82What a rubbish article.
Who was the idiot who posted a link to it ?
Re: Breakthrough: The Secret to Making Processors 1,000 Times Faster
#83Earlier quoted context omitted.
How about L1 cache (or even just L3 cache) measured in gigabytes? That won't increase the execution speed of individual instructions, but your effective processing power would increase dramatically.
The problem is that as cache size gets bigger, the associative memory lookup gets slower. There's a tradeoff.
What? Why is this, isn't memory indexed for direct access?
Re: Breakthrough: The Secret to Making Processors 1,000 Times Faster
#84This is Mashable talking about real technology: of course they're writing bull.
Re: Breakthrough: The Secret to Making Processors 1,000 Times Faster
#85Let me get this straight. Today, we have trouble dissapating the heat produced by a single die. To solve this problem, we are going to stack 1000 dies, and produce 1000x as much heat. Who cares about whether the heat can travel up the column- where is the improvement in cooling technology to remove 1000x the heat from the die stack?
I would assume the heat would be expected to ooze out the sides of each layer... e.g like the condiments leaking out the burger when you squeeze it :-)
Actually, this makes me think. The area now dissipating heat is much smaller (perimeter of the square * h, and used to be the area of the square). You have to dissipate the heat. The solution really can't be as simple as the article proposes.
Re: Breakthrough: The Secret to Making Processors 1,000 Times Faster
#86Earlier quoted context omitted.
The problem is that as cache size gets bigger, the associative memory lookup gets slower. There's a tradeoff.
What? Why is this, isn't memory indexed for direct access?
We're talking about cache, where the addresses of blocks in cache do not have a 1:1 mapping with addresses in memory.
Read the section on associativity: http://en.wikipedia.org/wiki/CPU_cache
Re: Breakthrough: The Secret to Making Processors 1,000 Times Faster
#87Great. But the IO is still orders of magnitudes away from the processor.
Faster CPU's are important in several areas, but for 99% of problems it's RAM and stable storage that are the bottleneck.
Re: Breakthrough: The Secret to Making Processors 1,000 Times Faster
#88Earlier quoted context omitted.
The point with 3d layout is that you can have shorter interconnects, which means far less resistive heating, and less junction loss. It also means that your path lengths can be shortened, possibly allowing you to bump up the frequency. Stacking stuff means you should be able to run cooler for the same amount of processing power. 1000x? I think that's probably BS. But I can see this being a significant win.
This makes me think of an interesting question- the back side of a die is raw silicon. How do you stack die and still interconnect? Do you sink metal through the bottom of the wafer?
Yes, through-silicon vias are metal-plated holes that go clear through the wafer ( http://en.wikipedia.org/wiki/Through-silicon_via ).
Re: Breakthrough: The Secret to Making Processors 1,000 Times Faster
#89Earlier quoted context omitted.
What? Why is this, isn't memory indexed for direct access?
We're talking about cache, where the addresses of blocks in cache do not have a 1:1 mapping with addresses in memory. Read the section on associativity: http://en.wikipedia.org/wiki/CPU_cache
You get to choose your associativity, you could build a direct-mapped 1GB L1 cache if you wanted. More fundamentally, a memory's access time grows with its capacity because the average and worst-case distances from a bitcell to the read/write port are longer.
Re: Breakthrough: The Secret to Making Processors 1,000 Times Faster
#90Earlier quoted context omitted.
> still have time for clock distribution... We are talking about pretty radical processor designs. Why not go asynchronous if we are talking about coordinating multiple layers of silicon?
Wouldn't a principle advantage of an actual, innovative 3D chip be better component distribution? That is, on average all the parts will be much closer to each other, than if they were arranged on a 2D surface.
From the images, it appears inter-chip connections run over the external borders. This increases the distances signals have to travel and limits the width of the buses. I am not familiar with the technical limits of building vertical buses connecting the various chips glued together, but I assume 1000+ bit wide buses would not be impossible, so, although limited, the limits seem pretty high. Optical interconnects may also be possible in such confined devices.
It will be interesting to watch. If real devices built with that technologies start showing in p and zSeries machines before 2015, we'll have some serious performance bump in high-end computers.