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SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

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Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#81

Post by lizknope »

gautamcgoel wrote: post #70
lizknope wrote: post #12

Earlier quoted context omitted.

They pay money just like any other customer of TSMC. SiFive has a lot of buzz in the industry. I wouldn't be surprised that TSMC wanted to work with them. But there are other intermediary companies that help startups group multiple chips from multiple companies together into a single mask. This is called a "shuttle" and allows the companies to split the costs of the masks (I've heard up to $30 million for 5nm) SiFive…

Can you list some of these shuttle companies? What are the most popular/reputable ones?

When I have worked at large companies we handled everything ourselves and dealt directly with the fabs.

When I worked at startups and smaller companies we have interacted with:

Global Unichip Corporation (I believe TSMC owns part of the company)

https://www.guc-asic.com/en-global

Open Silicon (they literally merged with SiFive to become OpenFive and made this chip in the article)

https://en.wikipedia.org/wiki/Open-Silicon

Uniquify

https://www.uniquify.com/

Socionext

https://www.socionext.com/en/

There are others but these are the 4 that I have dealt with.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#82

Post by brucehoult »

bogomipz wrote: post #52
lizknope wrote: post #10

Earlier quoted context omitted.

I'm in the semiconductor company. I don't really understand your question. Anyone can start a company and tape out a chip even in 5nm. My previous startup did something similar. We used an intermediate company between us and TSMC that specifically works with smaller companies. They (or TSMC) will bundle together 4 to 20 chips into a common mask as a "shuttle" run. Shuttle runs are really only used to get samples for…

>" Shuttle runs are really only used to get samples for the first version of your chip." Is a "tape out" the same thing as a shuttle run/sample chip run?

The only difference between a shuttle run and mass production is whether your chip is repeated 100 times in different parts of the wafer (surrounded by other people's chips) or a few thousand times completely covering the wafer with copies of just your chip.

The manufacturing process is identical either way.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#83

Post by manicpolymath »

chmod600 wrote: post #69
dragontamer wrote: post #27

Earlier quoted context omitted.

Electric cars have ONE battery with thousands of *cells*. I do realize that the colloquial term for "cell" is "battery" (ex: an AA cell is called a battery), but it becomes important to be precise with our words when talking about manufacturing. Small scale Li-ion does a protection-IC per cell (ex: cell phones), mostly because cell phones are so small they only use one cell. Larger scale Li-ion, such as Laptop batter…

I always thought the "cell" in "cellular phone" came from the network topology, not the battery format.

Oh it does come from the network region/cells. In fact in the old days when the phones were the size of an actual brick they were probably powered by a proper multi-cell battery. (Did I miss a joke?)

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#84

Post by dpe82 »

tsomctl wrote: post #77
dpe82 wrote: post #66

Earlier quoted context omitted.

Most of those chips would be standard commodity silicon components (think op-amps and such) as opposed to purpose-built automotive micro controllers.

Uh, no. There's a ton of dedicated integrated circuits that are highly optimized for one specific task, and which contain everything you need. For example, an ABS module is going to contain something like the L9396, which does signal conditioning for wheel speed sensors, and mosfet drivers for the solenoids. All in one little package configurable by SPI. And even the standard commodity silicon components are going to…

If there's a ton of dedicated circuits highly optimized for each specific task, then I don't know why there'd be 10+ of them per task as OP claims. :)

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#85

Post by tails4e »

bogomipz wrote: post #52
lizknope wrote: post #10

Earlier quoted context omitted.

I'm in the semiconductor company. I don't really understand your question. Anyone can start a company and tape out a chip even in 5nm. My previous startup did something similar. We used an intermediate company between us and TSMC that specifically works with smaller companies. They (or TSMC) will bundle together 4 to 20 chips into a common mask as a "shuttle" run. Shuttle runs are really only used to get samples for…

>" Shuttle runs are really only used to get samples for the first version of your chip." Is a "tape out" the same thing as a shuttle run/sample chip run?

Interesting fact, the term tape out comes from the way chips were physically laid out back in the early days. The chip layout was manually arranged using pieces of coloured tape on a large workspace/table. Once complete, this was photographed a layer at a time, which was then optically reduced to create the mask sets for manufacture. We still use the term tape out today, but no tape involved. I would love to have an experience of designing back during those days, it's so hands on.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#86

Post by bogomipz »

tails4e wrote: post #85
bogomipz wrote: post #52

Earlier quoted context omitted.

>" Shuttle runs are really only used to get samples for the first version of your chip." Is a "tape out" the same thing as a shuttle run/sample chip run?

Interesting fact, the term tape out comes from the way chips were physically laid out back in the early days. The chip layout was manually arranged using pieces of coloured tape on a large workspace/table. Once complete, this was photographed a layer at a time, which was then optically reduced to create the mask sets for manufacture. We still use the term tape out today, but no tape involved. I would love to have an…

Fascinating. So was each mask in a mask set individually taped to the work surface one at a time in order to be photographed?

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#87

Post by LennyWhiteJr »

Kliment wrote: post #80
mkl wrote: post #75

Earlier quoted context omitted.

I still don't understand how the car industry could have had this effect. How/why did all the different companies in the auto industry coordinate chip ordering/cancelling like that? Or was it a single company that they all order from? Or an unfortunate coincidence?

They hang out at the same parties. For some reason all the car industry execs were convinced that people would buy dramatically fewer cars in 2020. Because they have a religious aversion to holding any stock they decided to shift the risk over to their suppliers, fucking said suppliers over, as the car industry normally does when they expect demand shifts. The thing that made this particular time special as opposed t…

Great explanation, thank you!
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