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FPGA Design for Software Engineers

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Re: FPGA Design for Software Engineers

#81

Post by topspin »

lnsru wrote: post #46
topspin wrote: post #34

Earlier quoted context omitted.

Nice work. FPGA design appears to be very similar to GPU shader programming. First time I've read anything about FPGA design that connected. Usually FPGA stories get lost in data flow jargon and I learn nothing.

There is no programming in FPGA at all. You describe your hardware using hardware description languages like VHDL or Verilog.

You'll notice I didn't apply the term 'programming' to FPGA. Reading the post I noted this was a likely hang up among FPGA designers and carefully employed the preferred jargon. I imagine this sensitivity is the product of much frustration with forever being conflated with mere programmers. Must be awful.

Re: FPGA Design for Software Engineers

#82

Post by orbifold »

q3k wrote: post #58
lnsru wrote: post #50

I am curious, why System Verilog isn’t mentioned in this article. It is much much better than Verilog and is used in industrial applications. What I am missing are 2 topics: timing analysis and debugging. Static timing analysis and proper timing constrains are crucial for functional design. No tool can differentiate without constrains a slow signal signal toggling LED every 10 seconds from DDR3 533 MHz differential c…

> I am curious, why System Verilog isn’t mentioned in this article. It is much much better than Verilog and is used in industrial applications. Probably because it has very limited support in open source tooling, same as VHDL.

That is not true: Verilator is an excellent tool that compiles a large subset of synthesizable System Verilog to C++. Companies like Tesla use it and report speed ups of up to 40 compared to commercial tools. Similarly for vhdl there exists ghdl, which seems pretty feature complete and has an LLVM backend

Re: FPGA Design for Software Engineers

#83

Post by q3k »

orbifold wrote: post #82
q3k wrote: post #58

Earlier quoted context omitted.

> I am curious, why System Verilog isn’t mentioned in this article. It is much much better than Verilog and is used in industrial applications. Probably because it has very limited support in open source tooling, same as VHDL.

That is not true: Verilator is an excellent tool that compiles a large subset of synthesizable System Verilog to C++. Companies like Tesla use it and report speed ups of up to 40 compared to commercial tools. Similarly for vhdl there exists ghdl, which seems pretty feature complete and has an LLVM backend

Right, but these are simulators, while the article is looking for a language to both simulate and synthesize using open source tooling.

Yosys (which AFAIK is still the only non-toy open source synthesis tool) supports a _very_ small subset of SV, and does not support VHDL (at least in the open source version).

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