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ESP32-S31

espressif.com

71–80 of 207 posts

Re: ESP32-S31

#71
post #24

I'm interested in audio out because I dabble in musical instruments. What's the state of Bluetooth audio out on microcontrollers? Is low latency and high quality output possible?

Low latency in Bluetooth audio comes down to codecs and the best are proprietary. If you want to really cut down latency and need wireless with hardware like this, you could use a second ESP32 and send your own bitstream between them.

I've been experimenting with more-or-less this on the existing ESP32-S3 (well, to a smartphone/PC rather than a 2nd ESP32).

Practical bandwidth limits are in the ~72kb/s range with Bluetooth and a custom wire protocol, and Opus voice-mode encoding can't run in realtime beyond complexity 3; music encoding can't run at all. Maybe there's a more compute-friendly audio codec I'm not aware of, but as far as I know these chips just aren't quite powerful enough for high-quality music encoding, unfortunately. I'm hoping the S31 might be a bit better fit here (decent CPU boost + better SIMD).

Latency is still a bit rough with BT overhead. There might be some new options with LE audio on the S31 but I haven't found a way to get below ~80ms with the existing ESP32-S3 stack.

tl;dr, high quality voice is doable today with okay latency, music probably less so, maybe the S31 will be better

Re: ESP32-S31

#72
post #54
post #32

It being RISC-V is awesome, but how does it make sense that it's S series when S series have been Xtensa cores? Why is it not C series?

S has never implied Xtensa, and C doesn't imply RISC-V. That's a widely held misunderstanding. S, C, P, etc. are product categories, not ISAs. S devices are high performance SoCs; large feature set, high frequency, not the lowest power or cost. Just appending 1 to S3 is odd though. This MCU is step change for Espressif. S4 or something would make more sense.

Not saying you're wrong (appreciate the explanation) but S has been Xtensa and C is RISC-V; even if you don't imply, it's how the things have been. And given S2, S3, and C5 are all clocked at 240 MHz, the performance difference is kinda blur.

Re: ESP32-S31

#73

Earlier quoted context omitted.

>> And the CPU even has SIMD instructions! Yes, but it looks like there is no hardware floating point. The description of the CORDIC module indicates fixed-point calculations, which is consistent with the lack of any reference to floating point. I am happy the have CAN-FD and Motor PWM module, but nowhere did I see conversion times listed for the ADC. For motor control I demand 1uS conversion time or less, and in the…

Also why do you need 1uS for motor control? 1uS is 0.1 degrees of rotation at 16,666 RPM if I did the math right. I don't know much about motor control, is it normal to need that fast of feedback?

I similarly don't know much about motor control or hardware in general, but would this maybe open up multiplexing options?

Re: ESP32-S31

#74
post #53

I kind of wish these all weren't called ESP32. ESP8266 and ESP8285 -> ESP32 made sense, but now we have 10+ different versions with different features and different architectures. Kind of like how in every thread involving a Raspberry Pi Pico (RP2030/RP2350), there's always someone confusing it with the single board computer version. The ESP32 (Classic, usually WROOM-32E) is still usually what comes to mind when I he…

It signals ESP-IDF compatibility

They can signal that with numbers other than 32, the "ESP" part is what matters.

Re: ESP32-S31

#75
post #53

I kind of wish these all weren't called ESP32. ESP8266 and ESP8285 -> ESP32 made sense, but now we have 10+ different versions with different features and different architectures. Kind of like how in every thread involving a Raspberry Pi Pico (RP2030/RP2350), there's always someone confusing it with the single board computer version. The ESP32 (Classic, usually WROOM-32E) is still usually what comes to mind when I he…

Showing up in search results, or in this day and age LLM results, is still king. If your famous product is known as the ESP32, it doesn't hurt sales to spin other products off the same line. It might hurt clarity, glance value and many other things, but it will drive people to you.

Re: ESP32-S31

#76
post #36

Earlier quoted context omitted.

Theoretically, yeah. Though at 320Mhz, with only 2.4ghz wireless, even with two cores, I doubt it's going to get anywhere near the throughput to fill the gigabit connection.

Yeah, I’m not entirely sure what use cases there are which include both an ESP32 and gigabit networking.

About the only one I can think of is connectivity in electronically noisy situations. It's a lot easier to find gigabit sfp modules for linking with fiber than it is to find 100 mbit modules.

Re: ESP32-S31

#77
post #6

Good to have WiFi and wired ethernet on the same part again. Although we lost the MIPI support that the P4 dual-core RISC-V line has.

How does wired internet technically work on these chips? Is it just 8 dedicated GPIO pins?

You need a transceiver chip which then hooks up to the Ethernet jack.

Usually have to do this for any interface when the signals don't come in right at logic level, like CAN, RS-485...

although it's not always exactly 'just' logic level conversion.

Re: ESP32-S31

#78
post #61

Earlier quoted context omitted.

For what its worth, Espressif chips are open source, but yes, I wouldn't run national security or government devices on these. Edit: I take it back on OS comment, they are not OS but some components of the SDK are: https://zeus.ugent.be/blog/23-24/open-source-esp32-wifi-mac/

> Espressif chips are open source No they're not? Anyway I assume GP was asking due to procurement concerns, not security.

Corrected my comment, thank you. I mean, if productizing with them, global trade dynamics are certainly a supply chain risk factor, however, security concerns would be the primary reason such chips would be restricted from import.

Re: ESP32-S31

#79
post #72
post #54

Earlier quoted context omitted.

S has never implied Xtensa, and C doesn't imply RISC-V. That's a widely held misunderstanding. S, C, P, etc. are product categories, not ISAs. S devices are high performance SoCs; large feature set, high frequency, not the lowest power or cost. Just appending 1 to S3 is odd though. This MCU is step change for Espressif. S4 or something would make more sense.

Not saying you're wrong (appreciate the explanation) but S has been Xtensa and C is RISC-V; even if you don't imply, it's how the things have been. And given S2, S3, and C5 are all clocked at 240 MHz, the performance difference is kinda blur.

Espressif is all-in on RISC-V, expanding their portfolio of RISC-V devices where they previously had only XTensa: ESP32-S31 is the first big departure from the coincidental alignment of ISAs within their product structure and definitively ends further debate about what those letter designations mean.

BTW, S3 has an RISC-V core in addition to the XTensa cores. That's the part that's running in deep sleep.

In practice, most Espressif users barely know or care what ISA is in play: they have ESP-IDF and the Espressif libraries papering over the difference for nearly all purposes.

Re: ESP32-S31

#80
post #53

I kind of wish these all weren't called ESP32. ESP8266 and ESP8285 -> ESP32 made sense, but now we have 10+ different versions with different features and different architectures. Kind of like how in every thread involving a Raspberry Pi Pico (RP2030/RP2350), there's always someone confusing it with the single board computer version. The ESP32 (Classic, usually WROOM-32E) is still usually what comes to mind when I he…

It's like these for other families too, you've got your STM32, then you can get the sub-models ranging from entry-level STM32C0 to the full Linux chips like the STM32MP2, with lots of options in the middle
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