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Pure Silicon Demo Coding: No CPU, No Memory, Just 4k Gates

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Re: Pure Silicon Demo Coding: No CPU, No Memory, Just 4k Gates

#71

Post by immibis »

zahlman wrote: post #67
yoan9224 wrote: post #62

This is absolutely wild. Rendering graphics with just combinational logic and no frame buffer is the kind of constraint that breeds creativity. The HAKMEM sine/cosine generator is such an elegant choice - it's numerically stable in fixed-point and requires only adds and bit-shifts. Perfect for hardware. I used a similar approach once for generating test patterns in an FPGA. The fact that you can iterate on this in si…

> The fact that you can iterate on this in simulation, then deploy to actual silicon via Tiny Tapeout for $150 is honestly mind-blowing. We're living in the future. It's really cool but it doesn't seem practical at all. They aren't setting up print runs, just one-offs ( https://tinytapeout.com/faq/#how-many-chips-will-i-receive-c... ) and $150 could get you... many orders of magnitude more power than that. ... For th…

Tiny Tapeout's schtick is that for $150 you can get your chip design made at all. It's not a mass production run.

Remind me to participate in the next one!

Re: Pure Silicon Demo Coding: No CPU, No Memory, Just 4k Gates

#72

Post by immibis »

idiotsecant wrote: post #32
layer8 wrote: post #27

Earlier quoted context omitted.

Or maybe ChatGPT picked it up from common usage.

It was used occasionally before chatGPT but it has exploded since then.

Apparently ChatGPT speaks like lower-class Kenyans. You can guess why.

Re: Pure Silicon Demo Coding: No CPU, No Memory, Just 4k Gates

#73

Post by Joel_Mckay »

jacquesm wrote: post #63
Joel_Mckay wrote: post #57

Earlier quoted context omitted.

Hardware takes 20 years to learn how to build properly. Software takes 1 year under someone smart in a production environment. People that conflate the two... longer or more likely never.. =3

> Software takes 1 year under someone smart in a production environment. That's very funny.

Be honest, most Software people find utility in artifacts which are a mysterious black box with an emulated abstraction.

During a career role most have no idea "why" chips were designed and built a certain way, nor require this information to work within abstract domains.

In many ways, vibe-coders are the absurd optimization of a naive trajectory toward zero workmanship standards. =3

https://en.wikipedia.org/wiki/Five_stages_of_grief

Re: Pure Silicon Demo Coding: No CPU, No Memory, Just 4k Gates

#74

Post by RossBencina »

alfiedotwtf wrote: post #54
Neywiny wrote: post #10

Earlier quoted context omitted.

I recommend getting started like the author did: simulation first, then FPGA. Honestly FPGA will take you very far. I always get a kick out of being able to design my own SoC. "Hmmm I need 9 separate I2C ports... Ok, copy block, paste paste paste..." Or if you have an operation in software that's taking forever you can write an accelerator for it

Are there any open or at least standard FPGAs that the open source community flock to? Last time I looked into FPGAs, it was mostly closed architecture and proprietary tools

One flock-to is Lattice ICE40 series. Decent support from Yosys for hobby stuff at least. Possibly Go-win. You can develop for many of the affordable FPGAs with free versions of the proprietary tools. As for "closed architecture" it depends what you mean, the architecture of all FPGAs that I know of is documented, the tools show you how your design was mapped onto the hardware. The proprietary stuff includes the timing model that drives the static timing analysis and timing-aware place and route.

Re: Pure Silicon Demo Coding: No CPU, No Memory, Just 4k Gates

#75

Post by jayd16 »

RossBencina wrote: post #35
jayd16 wrote: post #13

Earlier quoted context omitted.

I don't know. Analog signal processing is clearly less memory than a register, no? So a line exists somewhere and I think it's way before no RAM.

> Analog signal processing is clearly less memory than a register, no? You are going to have a hard time doing analog signal processing with memoryless elements. In the linear domain all you can do is apply gain and mix signals together. If you work with memoryless nonlinearities you can do waveshaping, which is generally only useful when applied to special signals (e.g. sine waves). Any time you want to do frequency…

I would say that there's a difference between simply a stateful circuit using capacitors etc and a digital register, at least in so far as a "hey look what I made" kind of post.

I have no qualms saying a stateful device can have no memory in the addressable memory sense.

Re: Pure Silicon Demo Coding: No CPU, No Memory, Just 4k Gates

#76

Post by RossBencina »

jayd16 wrote: post #75
RossBencina wrote: post #35

Earlier quoted context omitted.

> Analog signal processing is clearly less memory than a register, no? You are going to have a hard time doing analog signal processing with memoryless elements. In the linear domain all you can do is apply gain and mix signals together. If you work with memoryless nonlinearities you can do waveshaping, which is generally only useful when applied to special signals (e.g. sine waves). Any time you want to do frequency…

I would say that there's a difference between simply a stateful circuit using capacitors etc and a digital register, at least in so far as a "hey look what I made" kind of post. I have no qualms saying a stateful device can have no memory in the addressable memory sense.

> I have no qualms saying a stateful device can have no memory in the addressable memory sense.

I'm not sure where addressable comes in. A digital register is literally a flip-flop (or a bank of flip-flops). It's wired into a larger circuit the same way that a capacitor is.

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