Transmeta made a technology bet that dynamic compilation could beat OOO super scalar CPUs in SPEC. It was wrong, but it was controversial among experts at the time. I’m glad that they tried it even though it turned out to be wrong. Many of the lessons learned are documented in systems conferences and incorporated into modern designs, ie GPUs. To me transmeta is a great example of a venture investment. If it would hav…
Did anyone try dynamic recompilation from x86 to x86? Like a JIT taking advantage of the fact that the target ISA is compatible with with the source ISA.
What happened to Transmeta, the last big dotcom IPO
71–80 of 156 posts
Re: What happened to Transmeta, the last big dotcom IPO
#72Earlier quoted context omitted.
I worked at Transmeta. I remember for the launch of one of the Crusoe-powered laptops, there was a bug that prevented the BIOS from booting Linux. Since the laptop was only going to run Windows ME, they didn’t fix it. Of course when Linus got a demo unit to play with, the first thing he did was try to install Linux on it. He let everyone know, and the bug was fixed soon there after.
Nice. Glad you were a part of it at the time?
Re: What happened to Transmeta, the last big dotcom IPO
#73Earlier quoted context omitted.
> However, if you add it onto a better CPU it’s a fine technique to bet on - case in point Apple’s move away from Intel onto homegrown CPUs. I don't think Apple is a good example here. Arm was extremely well-established when Apple began its own phone/tablet CPU designs. By the time Macs began to transition, much of their developer ecosystem was already familiar. Apple's CPUs are actually notably conservative when com…
> no special vector instructions (e.g. SVE) Wut - SVE and SME are literally Apple designs (AMX) which have been "back ported".
Literally no Apple CPUs meaningfully support SVE or SVE2. Apple adds what I would say is a relatively "conventional" matrix instructions (AMX) of their own, and now implements SME and SME2, but those are not equivalent to SVE (I call AMX "conventional" in the sense that a fixed-size grid of matrix compute elements is not a particularly new idea, versus variable-sized SIMD which is still quite rare. Really, the only arm64 design with "full fat" SVE support is Fujitsu's a64fx (512-bit vector size); everything else on the very short list of hardware supporting SVE is still stuck with 128-bit vectors.
Re: What happened to Transmeta, the last big dotcom IPO
#74> so IBM handled manufacturing of its first-generation CPUs. I'm curious: Is there a consensus on which startup companies achieved success using IBM as a fab? or if not a consensus, I'd settle for anecdotes too. My own company (which built 40G optical transponders) used them back in that era. While the tech was first rate, the pricing was something to behold.
Re: What happened to Transmeta, the last big dotcom IPO
#75I liked the Transmeta web page from before they launched. It was just bare HTML with no styling. It said: This page is not here yet. The product hype and lack of knowledge about what it was meant that nobody knew what to expect. In these hyped expectations, and with Torvalds on board, everyone expected that everything would be different. But it wasn't. A similar product launch was the Segway, where we went from this…
there are no secret messages in this html
there are no tyops in this html
which at the time I took as some inside joke.Re: What happened to Transmeta, the last big dotcom IPO
#76Earlier quoted context omitted.
Aren't modern CPUs, essetially, dynamic translators from x86_64 instruction set into internal RISC-like intsruction sets?
Folks like to say that, but that's not what's happening. The key difference is: what is an instruction set? Is it a Turing-complete thing with branches, calls, etc? Or is it just data flow instructions (math, compares, loads and stores, etc)? X86 CPUs handle branching in the frontend using speculation. They predict where the branch will go, issue data flow instructions from that branch destination, along with a speci…
Fixed guest branches just get turned into host branches and work like normal.
Indirect guest branches would get translated through a hardware jump address cache that was structured kind of like TLB tag lookups are.
Re: What happened to Transmeta, the last big dotcom IPO
#77Earlier quoted context omitted.
Not to the same level. Crusoe was, in many ways, more classic CISC than x86 - except it's microcode was actually doing dynamic translation to internal ISA instead of operating like interpreter in old CISCs. x86 ISA had the funny advantage of being way closer to RISC than "beloved" CISC architectures of old like m68k or VAX. Many common instructions translate to single "RISCy" instruction for the internal microarchite…
> Many common [x86] instructions translate to single "RISCy" instruction for the internal microarchitecture And then there are read-modify-write instructions, which on modern CPUs need two address-generation μops in addition to the load one, the store one, and the ALU one. So the underlying load-store architecture is very visible. There’s also the part where we’ve trained ourselves out of using the more CISCy parts o…
It's not too uncommon for each pipeline stage or so to have their own uop formats as each stage computes what it was designed to and culls what later stages don't need.
Because of this it's not that weird to see both a single rmw uops at, says the initial decode and microcode layer, that then gets cracked into the different uops for the different functional units later on.
Re: What happened to Transmeta, the last big dotcom IPO
#78Earlier quoted context omitted.
Folks like to say that, but that's not what's happening. The key difference is: what is an instruction set? Is it a Turing-complete thing with branches, calls, etc? Or is it just data flow instructions (math, compares, loads and stores, etc)? X86 CPUs handle branching in the frontend using speculation. They predict where the branch will go, issue data flow instructions from that branch destination, along with a speci…
> That said, I don't know what the Transmeta CPUs did. Maybe they had a low-level instruction set that had all sorts of hacks to help the translation layer avoid the problems of branch destination translation. Fixed guest branches just get turned into host branches and work like normal. Indirect guest branches would get translated through a hardware jump address cache that was structured kind of like TLB tag lookups…
> Fixed guest branches just get turned into host branches and work like normal.
How does that work in case of self-modifying code, or skewed execution (where the same x86 instruction stream has two totally different interpretations based on what offset you start at)?
Re: What happened to Transmeta, the last big dotcom IPO
#79Earlier quoted context omitted.
I worked at Transmeta. I remember for the launch of one of the Crusoe-powered laptops, there was a bug that prevented the BIOS from booting Linux. Since the laptop was only going to run Windows ME, they didn’t fix it. Of course when Linus got a demo unit to play with, the first thing he did was try to install Linux on it. He let everyone know, and the bug was fixed soon there after.
Back in the day, Linux was less tolerant of incorrect behavior than Windows 9x was, and would crash, terminate a process, or otherwise surface errors at times when Windows 9x would just keep going until the bugs corrupted memory or similar. Having Linus aboard as a technical advisor, soneone to whom you can say "hey, the CPU is crashing here, what's the kernel trying to do at that spot?", alone, probably would have b…
Re: What happened to Transmeta, the last big dotcom IPO
#80Transmeta made a technology bet that dynamic compilation could beat OOO super scalar CPUs in SPEC. It was wrong, but it was controversial among experts at the time. I’m glad that they tried it even though it turned out to be wrong. Many of the lessons learned are documented in systems conferences and incorporated into modern designs, ie GPUs. To me transmeta is a great example of a venture investment. If it would hav…
That's kind of the bet they made, but misses a key point. Their fundamental idea was that by having simpler CPUs, they could iterate on Moore's law more quickly. And eventually they would win on performance. Not just on a few speculative edge cases, but overall. The dynamic compilation was needed to be able to run existing software on it. The first iterations, of course, would be slower. And so their initial market,…