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AMD's Turin: 5th Gen EPYC Launched

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Re: AMD's Turin: 5th Gen EPYC Launched

#71
post #25

At 1:11 in the video, there's a chart of the TDP (which I looked for in the text but couldn't find). At 125-500W, these things run very hot.

The cores are spread out over roughly 1200 mm² of silicon and the IO die seems to have grown again (maybe 500ish mm²?). So at just 0.3 W/mm² this is pretty cozy. The desktop parts have 3x higher power density.

Re: AMD's Turin: 5th Gen EPYC Launched

#72
post #45

Earlier quoted context omitted.

Whats wrong with an arbitary 16 digit number?

I'm sure each of the products has a numeric identifier. One can use that if they feel pressed by the "childish" names.

AMD CPUs have pretty small numbers for that, e.g. 100-000000651 or 100-000000789. They almost look wrong with so many zeroes. Zen/+/2 parts have part numbers like YD160XBCM6IAE (which is similar to the part numbers of much older AMD CPUs, which is apparently the AMD Ordering Part Number, OPN, scheme, and every digit codes information about the CPU). Zen 3 started with the new scheme, which just seem to be sequential development numbers. E.g. 3800X is 100-000000022. Here's a list: https://mkdev.info/?p=1245

Re: AMD's Turin: 5th Gen EPYC Launched

#73

Truly mind boggling scale. Twenty years ago we had just 1-2 cores per CPU, so we were lucky to have 4 cores in a dual socket server. A single server can now have almost 400 cores. Yes, we can have even more ARM cores but they don't perform as well as these do, at least for now.

700+ threads over 2 cores, can saturate 2 400gbe Nic's 500 wats per chip (less than 2 wats per thread)... All of that in a 2U package.... 20 years ago that would have been racks of gear.

> 700+ threads over 2 cores

I assume you mean 2 sockets.

Re: AMD's Turin: 5th Gen EPYC Launched

#74
post #69

Earlier quoted context omitted.

Ehhhh the MAJC 5200 was generally available in 1999 and I am sure even older designs could be found if we were to dig deep enough. Their market share would also need some digging too. To quote the announcement: "two VLIW (very long instruction word) microprocessors on a single piece of silicon"

Power and PA-RISC shipped servers, though. MAJC on the other hand > Sun built a single model of the MAJC, the two-core MAJC 5200, which was the heart of Sun's XVR-1000 and XVR-4000 workstation graphics boards.

MAJC: https://en.m.wikipedia.org/wiki/MAJC

Why have I not heard of those before?

Re: AMD's Turin: 5th Gen EPYC Launched

#75
post #65

Earlier quoted context omitted.

1-3rd gen Epycs can be had super cheap, but the motherboards are expensive. Also not worth getting anything less than 3rd gen unless you're primarily buying them for the pcie lanes and ram capacity - a regular current gen consumer CPU with half - a quarter of the core count will outperform them in compute while consuming significantly less power.

When buying used Epycs you have to contend with them possibly being vendor-locked to a specific brand of motherboard as well. https://www.servethehome.com/amd-psb-vendor-locks-epyc-cpus-...

They sell this vendor lock-in "feature" as enhanced security?

Re: AMD's Turin: 5th Gen EPYC Launched

#76

Truly mind boggling scale. Twenty years ago we had just 1-2 cores per CPU, so we were lucky to have 4 cores in a dual socket server. A single server can now have almost 400 cores. Yes, we can have even more ARM cores but they don't perform as well as these do, at least for now.

700+ threads over 2 cores, can saturate 2 400gbe Nic's 500 wats per chip (less than 2 wats per thread)... All of that in a 2U package.... 20 years ago that would have been racks of gear.

I think those really 2 watts per thread are a lot more important than what us home users usually think. Having to deliver less power and having to dissipate less watts in form of heat in a data centre are really good news to its operative costs, which is usually a lot bigger than the cost of the purchase of the servers

Re: AMD's Turin: 5th Gen EPYC Launched

#77
The weirdest one of the bunch is the AMD EPYC 9175F: 16 cores with 512MB of L3 cache! Presumably this is for customers trying to minimize software costs that are based on "per-core" licensing. It really doesn't make much sense to have so few cores at such an expense, otherwise. Does Oracle still use this style of licensing? If so, they need to knock it off.

The only other thing I can think of is some purpose like HFT may need to fit a whole algorithm in L3 for absolute minimum latency, and maybe they want only the best core in each chiplet? It's probably about software licenses, though.

Re: AMD's Turin: 5th Gen EPYC Launched

#78
post #34

[flagged]

Naples, Rome, Milan, Genoa, and Turin are just cities in Italy; I'm not sure what's childish about that. They have to use something for codenames.

Ah, I was unsure if it was named after the city or the [Tolkien character](https://en.wikipedia.org/wiki/T%C3%BArin_Turambar).

Re: AMD's Turin: 5th Gen EPYC Launched

#79
post #45

Earlier quoted context omitted.

I'm sure each of the products has a numeric identifier. One can use that if they feel pressed by the "childish" names.

AMD CPUs have pretty small numbers for that, e.g. 100-000000651 or 100-000000789. They almost look wrong with so many zeroes. Zen/+/2 parts have part numbers like YD160XBCM6IAE (which is similar to the part numbers of much older AMD CPUs, which is apparently the AMD Ordering Part Number, OPN, scheme, and every digit codes information about the CPU). Zen 3 started with the new scheme, which just seem to be sequential…

They left enough leading zeros in there to make room for future revisions until the death of the universe.

Re: AMD's Turin: 5th Gen EPYC Launched

#80
post #77

The weirdest one of the bunch is the AMD EPYC 9175F: 16 cores with 512MB of L3 cache! Presumably this is for customers trying to minimize software costs that are based on "per-core" licensing. It really doesn't make much sense to have so few cores at such an expense, otherwise. Does Oracle still use this style of licensing? If so, they need to knock it off. The only other thing I can think of is some purpose like HFT…

Plenty of applications are single threaded and it's cheaper to spend thousands on a super fast CPU to run it as fast as possible than spend tens of thousands on a programmer to rewrite the code to be more parallel.

And like you say, plenty of times it is infeasible to rewrite the code because its third party code for which you don't have the source or the rights.

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