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Intel to set its FPGA unit free to pursue its own path

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Re: Intel to set its FPGA unit free to pursue its own path

#71

Post by SilverBirch »

aleph_minus_one wrote: post #32
SilverBirch wrote: post #23

Yeah it was really funny watching Intel buy Altera at the same time that they were spinning out McAfee and thinking “well we’ll see how long this lasts…” Big chunk of the team from Altera are at AMD now anyway. Hopefully they finally get back to innovating on the actual FPGA now. I’m so tired of the hardened rubbish and cpu integrated rubbish.

> I’m so tired of the hardened rubbish and cpu integrated rubbish. Was there actually a way to access a CPU-integrated FPGA as an "ordinary" user/customer (i.e. not a "special customer")?

No, because they screwed up the tapeout of EMIB (they literally didn't even test it), and the value proposition was terrible - hey guys how do you fancy an Intel Xeon with some FPGA fabric on it - it's really exciting, all you do is you turn off a couple of your cores to reduce the CPU power consumption and then you can turn on 10k LUTs!

Re: Intel to set its FPGA unit free to pursue its own path

#73

Post by SilverBirch »

JonChesterfield wrote: post #72

How do the xilinx and altera systems compare in practice? Learn how FPGAs work is somewhere on my todo list and they seem to be the main two options.

Xilinx and Altera fundamentally do the same thing to an almost silly extent. There are a handful of fundamental building blocks that make up an FPGA, and in every case Xilinx's implementation differs from Altera, but in trivial ways. Altera have an Adaptive Logic module whereas Xilinx have a Configurable Logic Block. They're really just look up tables.

So where the rubber meets the road is how good the tooling is and how well they execute on their tapeout. Xilinx has been much better executing their plans since Intel bought Altera.

Re: Intel to set its FPGA unit free to pursue its own path

#74

Post by sitkack »

hobo_mark wrote: post #69
mips_r4300i wrote: post #9

Thank goodness. I've been expecting this ever since Intel bought Altera, they just stuck with it a couple years longer than I figured. They focused solely on the high end, but it turns out nobody really wants FPGA fabric on a CPU. You can already do acceleration over a PCI express link, and that's what you more often do with embedded applications where the CPU is acting more like a dispatch controller than doing the…

> They have better tools, documentation, and support than Gowin, who is a recent Chinese FPGA upstart using stolen Lattice IP and hires. Naive of me to ask, but how are they allowed to sell anywhere outside of China?

> stolen Lattice IP and hires

If this is true, then the bitstream for Gowin and Lattice parts would be similar and both are being actively reverse engineered to be supported by OSS tools.

It would be nice to see more evidence of this.

Re: Intel to set its FPGA unit free to pursue its own path

#75

Post by sitkack »

rwmj wrote: post #68
mikepavone wrote: post #54

Earlier quoted context omitted.

Intel does have the Cyclone 5 SoC which integrates Cortex-A9 cores much like the Zynq 7000 series. That product predates the acquisition though and they don't seem to have released anything to compete with newer entries in the Zynq lineup

But the bet was customers would buy Xeons with an FPGA block that would "do magic". What magic it would do and how you'd program it in a sane way was never specified in great detail. In any case for those that really want this it turns out you can put the FPGA on the end of a regular PCIe link and get all the same benefits. Edit: By the way there is some niche research of the FPGA in core (which don't work if the FPG…

Intel suffers from the build it and they will come flaw of engineering.

I want multiple FPGAs in the CPU. Replace the PMU with an FPGA, replace the MMU with an FPGA, and by replace I mean augment and extend. Of course an FPGA can't do all the work of fixed blocks.

The ultimate problem is politics inside organizations and the lack of any sort of concrete creative thinking.

That Intel isn't incorporating Altera into IFS and allowing IFS customers to include FPGA fabric into their designs is predictable but both astonishing.

x86 and Altera as library IP only available on IFS would give them another 10 years of runway.

Intel had the same market segmentation and lack of imagination in how they applied Optane. Heck, Optane should have had FPGA fabric in each dimm. It appears that each sub-sku has their own fiefdom and their own P&L that ignores ecosystem effects.

Intel needs to be cleaned out.

Re: Intel to set its FPGA unit free to pursue its own path

#76

Post by sitkack »

ethbr1 wrote: post #60
glitchc wrote: post #51

Earlier quoted context omitted.

Sounds like intel is mismanaged.

It certainly was. It remains to be seen if it is. If they'd been made a performant (as in, non-x86) low-end CPU, then they wouldn't have lost mobile and be competing with ARM now. Intel of the past few decades learned the wrong lesson from their history. You can climb the value chain to riches, but once you're at the top you still need to seed the earth for the next generation of profits. And that means cheap entry p…

The low end always eats the high end, always. Intel sold StrongARM to Marvell and that is some of the Arm IP they are fighting against in hyperscaler space.

https://www.theregister.com/2006/06/27/intel_sells_xscale/

https://www.networkworld.com/article/3574013/marvell-exits-t...

Re: Intel to set its FPGA unit free to pursue its own path

#77

Post by Aromasin »

SilverBirch wrote: post #73
JonChesterfield wrote: post #72

How do the xilinx and altera systems compare in practice? Learn how FPGAs work is somewhere on my todo list and they seem to be the main two options.

Xilinx and Altera fundamentally do the same thing to an almost silly extent. There are a handful of fundamental building blocks that make up an FPGA, and in every case Xilinx's implementation differs from Altera, but in trivial ways. Altera have an Adaptive Logic module whereas Xilinx have a Configurable Logic Block . They're really just look up tables. So where the rubber meets the road is how good the tooling is an…

Altera were roadblocked by relying on Intel nodes. Their new product lines (Agilex 9/7/5/3) are excellent however, despite being 3 or 4 years too late to the market. I've been lucky enough to have early access to them. It's going to be an uphill battle for Altera to win back lost business but based on current performance, and looking at AMDs roadmaps, I wouldn't put it past Altera to take the lead again.

Re: Intel to set its FPGA unit free to pursue its own path

#78

Post by AtlasBarfed »

rthomas6 wrote: post #37
mips_r4300i wrote: post #9

Thank goodness. I've been expecting this ever since Intel bought Altera, they just stuck with it a couple years longer than I figured. They focused solely on the high end, but it turns out nobody really wants FPGA fabric on a CPU. You can already do acceleration over a PCI express link, and that's what you more often do with embedded applications where the CPU is acting more like a dispatch controller than doing the…

> nobody really wants FPGA fabric on a CPU. Not true... Xilinx sells a lot of their Zynq, MPSoC, and RFSoC chips. Though I guess those are more CPU on an FPGA.

Pretty sure the emulator community would be pretty psyched about a consumer priced fpga.

Re: Intel to set its FPGA unit free to pursue its own path

#79

Post by bcrl »

FullyFunctional wrote: post #53
hutzlibu wrote: post #49

Earlier quoted context omitted.

What happened with it? Wikipedia is very thin on the details. Did it simply not work out in mass production, or was it not considered worth it anymore as CPU and GPUs advanced?

My moles claim they simply couldn't get the software to work.

My understanding is that the hardware turned out to use way more power than expected. The whole premise of the design was that the extra registers between logic stages were "free". In the real world, pipelining has a significant power cost.

Re: Intel to set its FPGA unit free to pursue its own path

#80

Post by FullyFunctional »

bcrl wrote: post #79
FullyFunctional wrote: post #53

Earlier quoted context omitted.

My moles claim they simply couldn't get the software to work.

My understanding is that the hardware turned out to use way more power than expected. The whole premise of the design was that the extra registers between logic stages were "free". In the real world, pipelining has a significant power cost.

Are you talking about Achronix? Because they certainly did tell me that power was the reason they bailed on their original approach.

Space-Time ran hot, but I don’t see why they would be using more flip-flops than with a conventional FPGA. Also my sources were pretty clear on the cause of their failure.

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