Earlier quoted context omitted.
DDR5 has enough ECC on chip to make errors effectively impossible. It doesn't provide error data to the CPU, though, so errors in transit can still occur. This is really unlikely, though, and anything not mission-critical will no longer need the extra ECC computation on the CPU-side. (DDR5 encapsulates the memory controller).
source on that ? Did anyone tested that ? > This is really unlikely, though, and anything not mission-critical will no longer need the extra ECC computation on the CPU-side. ECC computation is done in hardware anyway
Of course this is assuming random cosmic ray bit flips, not faulty hardware. And it's speaking cost-wise from the manufacturer's perspective. I'd personally like full ECC to just be the standard.