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Nvidia R&D chief on how AI is improving chip design

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Re: Nvidia R&D chief on how AI is improving chip design

#71

Post by maxwells-daemon »

marginalia_nu wrote: post #44
maxwells-daemon wrote: post #36

I work on this team! (Specifically: applied deep learning research, chip design). It's a shame to see so many people dismissing this work as marketing. I see lots of clever people working hard on really novel and interesting stuff, and I really do think that ML has real potential to customize a design much more "deeply" than traditional automation tools.

This is directed at AI marketing in general: "AI" has been used to market so much nonsense it's probably becoming a problem communicating actual interesting uses of AI. I very much get a dot com vibe off it, like nobody on the team knows how it works but we're sure we're gonna be rich somehow! In my head, I've begun substituting AI with "wizards" when I read it. It's very much the sort of problems crypto is having. S…

I guess so, but the fact of the matter is that ML/AI is actually, right now, doing useful things that would have been impossible 10 years ago. I don't think I could say the same about crypto (as distinct from cryptography).

Re: Nvidia R&D chief on how AI is improving chip design

#72

Post by maxwells-daemon »

CreateAccntAgn wrote: post #62
maxwells-daemon wrote: post #36

I work on this team! (Specifically: applied deep learning research, chip design). It's a shame to see so many people dismissing this work as marketing. I see lots of clever people working hard on really novel and interesting stuff, and I really do think that ML has real potential to customize a design much more "deeply" than traditional automation tools.

Any word on how the accuracy/quality of final results compare to traditional flows? Are process variations handled differently (with regards to training or modelling) compared to IR? I assume traditional vendors (CDNS/SNPS/MENT) all have (or working on) AI driven tools as well. How do they compare?

In general, a function approximation solution like deep learning does worse on cases where exhaustively finding the exact optimum is possible (small combinatorial problems), but can be applied to much larger instances than the exact algorithms can.

Re: Nvidia R&D chief on how AI is improving chip design

#73

Post by areskay3 »

rektide wrote: post #2

Did nvidia just promise us singularity? :) Hard to read a talk like this from a pulpit & not see shout outs to the incredibly super-fantastic open-source innovative projects like OpenROAD which have been shipping amazingly well-routed-by-AI chips for a while now. There's papers you can cite, galore, many open source designs[1]. It's not like Nvidia is promising anyone else will benefit from this work. This seems to b…

All of the work discussed is published to some extent. References are in the slides

https://arxiv.org/pdf/2012.10597.pdf

https://research.nvidia.com/publication/2020-07_grannite-gra...

https://research.nvidia.com/sites/default/files/pubs/2020-07...

https://ieeexplore.ieee.org/document/8920342

Re: Nvidia R&D chief on how AI is improving chip design

#74

Post by qayxc »

jiggawatts wrote: post #47
qayxc wrote: post #35

Earlier quoted context omitted.

> The resolution with 64-bit floats (let alone integers) would be absurd, roughly a million times finer-grained still. Careful there! Floating point numbers do not form a proper field, not even a semi-group. Due to the uneven distribution of elements, the field axioms don't hold (e.g. both commutativity and distributivity can be violated) and great care has to be taken to assure the numeric stability of computations.

My physics professor had some good examples of how numeric precision vastly outstrips reality: if modelling a 1m iron bar using 32-bit numbers, the error in length is substantially less than a dust mote landing on the end of it. It's about the same as a virus (not a bacterium) on the end... or not. The oil from a fingerprint is thicker. The mere presence of a human in the room will warm up the iron rod enough to caus…

> [1] floating point numbers and integers are obviously different, but the concepts are the same.

No they're not. That's the entire point. 32 bit IEEE floats get you 6 to 9 significant digits, whereas 64 bit IEEE floats get you 15 to 17 significant digits. Loss of significance and catastrophic cancellation are real problems in numerical analysis.

Physics in particular doesn't often have closed form solutions, so you're forced to use iterative approximations. Same goes for large matrix operations, which is why you actually have to be very careful with the algorithm you choose and the order of operations.

If you're still not convinced, feel free to try it yourself:

  #include 
  #include 
  #include 
  #include 

  // solve ax^2+bx+c=0
  template auto
  solve_quadratic(T const& a, T const& b, T const& c) -> std::tuple {
    auto t = std::sqrt(b*b - T(4)*a*c);
    return {(-b + t) / (T(2)*a), (-b - t) / (T(2)*a)};
  }

  int main() {
    std::cout (a, b, c);
      std::cout (a, b, c);
      std::cout
Even 64-bit IEEE floats don't help if you use the standard quadratic formula. Note that you can improve the 32-bit case above significantly by reformulating the solution to

  template auto
  solve_quadratic(T const& a, T const& b, T const& c) -> std::tuple {
    auto sign_b = b
This simple change will yield the precise result (within the fp32 precision) for x1 and x2 with a=1, b=200, c=-0.000015 (i.e. the error of ax²+bx+c will be lower than the 9 max significant digits).

However this won't help with the second (64-bit) example, which will still be wrong after the 8th digit (i.e. well within the supposed 12 to 15 significant digits of a 64-bit IEEE float).

Also note that in both cases all numbers involved have less significant digits than supported by the respective FP format. Just to give you a little insight on why available bits ≠ precision in floating point maths.

Re: Nvidia R&D chief on how AI is improving chip design

#75

Post by Taniwha »

atq2119 wrote: post #58
Taniwha wrote: post #32

Earlier quoted context omitted.

So here's my autorouter first-guess analog computer design: On a basketball court create a pile of metal plates with bar codes and hooks, each one represents a gate, robot uses rubber bands of sizes vaguely representing timing budget from synthesis to hook the gates together. Robot picks up the whole thing using rubber bands representing the external ports and gives the whole thing a few shakes. Puts it all back down…

What you've described is actually for placement, not routing, and is in fact a good analogy for the first step in many placement algorithms. Interestingly, placement is much harder than routing from a complexity theory point of view (specifically, there are fairly strong inapproximability results for placement-style problems).

true - most chip tools I've used for layout do both place and route (and iterate, moving std cells apart to create routing resources) so I've always sort of thought of place&route as a single thing (though I've also interrupted it before initial routing to do scan insertion)

Re: Nvidia R&D chief on how AI is improving chip design

#76

Post by kraussvonespy »

maxwells-daemon wrote: post #36

I work on this team! (Specifically: applied deep learning research, chip design). It's a shame to see so many people dismissing this work as marketing. I see lots of clever people working hard on really novel and interesting stuff, and I really do think that ML has real potential to customize a design much more "deeply" than traditional automation tools.

A quick tangent if you have time and can discuss it: some really interesting, effective and odd antenna designs came from AI:

https://ti.arc.nasa.gov/m/pub-archive/1244h/1244%20(Hornby)....

Have there been any odd, surprising or wildly efficient chip designs that have come out of the AI designs?

Re: Nvidia R&D chief on how AI is improving chip design

#77

Post by jiggawatts »

hardolaf wrote: post #63
jiggawatts wrote: post #55

Earlier quoted context omitted.

The exact same arguments were made by CAD people insisting on 64-bit maths for OpenGL. They were wrong. They too were working on projects worth billions of dollars, over decades, where mistakes were very costly. Your link to a "DRC set" doesn't mean much to me out of context. I see some basic looking code with small-ish numeric constants in it. So what? This is not that different to the input to a simple physics simu…

So let's get this straight. You know nothing about this area and you assume the experts in it are wrong? Do you know what happens if you accidentally couple lines during one of the manufacturing steps? The wafer can, in the absolute worst case scenario, explode from super heating destroying not just the wafer but potentially the entire chamber it is in (any defect beyond what was designated as allowable by the design…

> Do you know what happens if you accidentally couple lines during one of the manufacturing steps?

I understand the consequences. I also understand both both physics and computer science. A 32-bit integer is sufficient to subdivide something the size of a wafer mask to well under the wavelength of the light used for photolithography. There is literally no way for additional precision to matter for things like "coupling lines". It is impossible.

See for yourself: https://www.wolframalpha.com/input?i=3+cm++*+2%5E-32

Iterated algorithms are a different beast entirely, but there are fixed-point or integer algorithms that sidestep these issues.

You cannot imagine the volume of computer science research that has been written on shape-shape intersections in both 2D and 3D! Literal textbooks worth. Hundreds if not thousands of PhD-level papers. The sheer intellectual effort that has gone into optimisations in this space is staggering.

Hence my incredulity. I've worked with 128-bit numbers and even arbitrary-precision numbers, but only in the context of computational mathematics. There are no "physics constraints" in mathematics to limit the benefit of additional range or precision.

Also, the financial argument doesn't hold water either. Modern chips have tens of billions of features. The data volume can exceed the size of main memory of even the largest computers. Data representation efficiency and simulation speed absolutely would have tangible business benefits: faster iteration cycles, lower simulation cost, better optimisation solutions, etc...

This is literally the point of the article -- being able to do things in GPUs using their native 32-bit maths capabilities is a huge benefit to the chip design workflow. This requires clever algorithms and data structure design. You can't be wasteful because "it feels safer" if you have a budget of 24 GB (or whatever) to squeeze the mask data into.

> assume the experts in it are wrong?

Yes! Something I've noticed is that there is surprisingly little "cross pollination" between fields. You can have very smart people in one industry blithely unaware that another industry has solved their "very hard problem". I've seen this with biology, physics, medicine, etc...

How many chip design automation experts have also done low-level game engine programming? Maybe half a dozen in the whole world? Less?

Re: Nvidia R&D chief on how AI is improving chip design

#78

Post by bsder »

gchadwick wrote: post #50
bsder wrote: post #41

Earlier quoted context omitted.

> Can you explain why such large numbers are required? Absolutely. Even if you start with 32 bits, you often have polygons with many sides. In the worst case, you are modeling a "circle" and have to increase your precision to enough level to be accurate (please note that nobody in the right mind in VLSI would ever draw a "circle"--however, you wind up with an "implied" one due to DRC, more down below ...) The problem…

Of course when you're doing such intersection calculations you know the things you're intersecting are very close. You don't need a general method that can test arbitrarily sized and spaced polygons against each other. You need a method to determine what is sufficiently close to each other to be worthy of a more detailed check. Then a more specific method to do this check. You could use 32 bit integers with all shape…

> You need a method to determine what is sufficiently close to each other to be worthy of a more detailed check.

Your line sweep data structure effectively already does that. I recommend reading the Hobby paper and thinking about how it works. And then you should think about how you differentiate inside from outside when you union/difference your polygons.

Any segments in the line sweep data structure simultaneously have already demonstrated that they need the detailed check.

If you want to argue this, you're going to need to study up on about 40 years of prior art. Given how much money this is worth and how many really smart people went after it (it basically drove the field of Computational Geometry for decades), the probability of you contributing something new to the current algorithms is basically zero.

However, the probability of you contributing something new to parallel DRC algorithms is really quite decent. Nobody I know of has yet come up with "good" parallel algorithms for DRC--most of them are hacks that quite often break down when they hit even common cases.

Being able to handle DRC on a billion VLSI polygons/10 billion line segments in a parallel fashion would be quite an advance, and the field is waiting for it.

Re: Nvidia R&D chief on how AI is improving chip design

#79

Post by jiggawatts »

jiggawatts wrote: post #43
bsder wrote: post #41

Earlier quoted context omitted.

> Can you explain why such large numbers are required? Absolutely. Even if you start with 32 bits, you often have polygons with many sides. In the worst case, you are modeling a "circle" and have to increase your precision to enough level to be accurate (please note that nobody in the right mind in VLSI would ever draw a "circle"--however, you wind up with an "implied" one due to DRC, more down below ...) The problem…

Disclaimer: I have zero silicon design experience. However, I have designed computer game engines that use 32-bit floats throughout and encountered rounding errors in practice. I’ve found that there’s always a solution that avoids the need to go past 64 bits, and even that is a last resort. So for example the circle could be approximated with a polygon. Or fixed-point arithmetic can be used. Or simply use a quad-tree…

Replying to myself to add:

Here's a Design Rule Checking (DRC) paper that mentions using 32-bit floats for things like checking distances between polygonal traces: https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.49...

If 32-bit is sufficient, then 64-bit definitely is, even for the latest & greatest silicon processes...

Re: Nvidia R&D chief on how AI is improving chip design

#80

Post by blihp »

andrepd wrote: post #45
blihp wrote: post #13

Earlier quoted context omitted.

> The chip design itself should be the secret sauce. Not the tools you make the chip with. The secret sauce is generally whatever gives one a competitive advantage. Businesses typically open things up when the want to reduce the cost of something and/or cause pain for someone else (i.e. killing their cash cow), not because they're benevolent and want to share. > I challenge you to answer your own question in reverse:…

The GP said nothing about "benevolence", he was arguing it is in the interest of NVidia

I suspect they would disagree with what's in their best interest. Most large businesses (especially nVidia) operate with a zero-sum mindset: they're not winning unless someone else is losing. To them, sharing information when not absolutely necessary is losing.
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