I think I remember reading an Intel article about something like this not too long ago. You can't just do this because of a few factors. When you start stacking the die like this, the latency grows. You now have to wait for signals to travel up through multiple processor die before it gets to the die that will process the instruction. It's this reason that you end up with diminishing returns when making processors "t…
... or stack a couple dozen gigabytes of L1 cache through a ridiculously wide internal bus. Not all chips would be processors.