71–80 of 82 posts
Just wanted to point out that 3nm or 2nm are nothing but the marketing terms. The physical channel length will continue to remain at around 10 nm in this decade, irrespective of the device architecture. See Fig. 1.2 of my PhD thesis: https://etheses.whiterose.ac.uk/22492/1/Novel%20Approaches%2...
Just wanted to point out that 3nm or 2nm are nothing but the marketing terms. The physical channel length will continue to remain at around 10 nm in this decade, irrespective of the device architecture. See Fig. 1.2 of my PhD thesis: https://etheses.whiterose.ac.uk/22492/1/Novel%20Approaches%2...
Also, how is that not false advertising then? If I’m told a device is 5nm, and that traditionally meant the gate length, why isn’t it a lie when they’re actually 10nm or whatever? We need to stop calling it “marketing terms” and call it what it is: lies. Just because everyone does it doesn’t make it right.
Just wanted to point out that 3nm or 2nm are nothing but the marketing terms. The physical channel length will continue to remain at around 10 nm in this decade, irrespective of the device architecture. See Fig. 1.2 of my PhD thesis: https://etheses.whiterose.ac.uk/22492/1/Novel%20Approaches%2...
Why is that? What’s the point in calling it “3nm” when it’s not? Also, how is that not false advertising then? If I’m told a device is 5nm, and that traditionally meant the gate length, why isn’t it a lie when they’re actually 10nm or whatever? We need to stop calling it “marketing terms” and call it what it is: lies . Just because everyone does it doesn’t make it right.
https://en.wikipedia.org/wiki/Category:Open_microprocessors
The IBM A2 and the UltraSPARC T2 look like sane choices. Perhaps there is a suitable RISC-V.
So then comparing processes, we could say that process X can do 54255 chips per square meter and process Y can do 83802 chips per square meter.
Just wanted to point out that 3nm or 2nm are nothing but the marketing terms. The physical channel length will continue to remain at around 10 nm in this decade, irrespective of the device architecture. See Fig. 1.2 of my PhD thesis: https://etheses.whiterose.ac.uk/22492/1/Novel%20Approaches%2...
Why is that? (Sorry, the paper is beyond my understanding)
Just wanted to point out that 3nm or 2nm are nothing but the marketing terms. The physical channel length will continue to remain at around 10 nm in this decade, irrespective of the device architecture. See Fig. 1.2 of my PhD thesis: https://etheses.whiterose.ac.uk/22492/1/Novel%20Approaches%2...
Why is that? What’s the point in calling it “3nm” when it’s not? Also, how is that not false advertising then? If I’m told a device is 5nm, and that traditionally meant the gate length, why isn’t it a lie when they’re actually 10nm or whatever? We need to stop calling it “marketing terms” and call it what it is: lies . Just because everyone does it doesn’t make it right.
Earlier quoted context omitted.
Why is that? What’s the point in calling it “3nm” when it’s not? Also, how is that not false advertising then? If I’m told a device is 5nm, and that traditionally meant the gate length, why isn’t it a lie when they’re actually 10nm or whatever? We need to stop calling it “marketing terms” and call it what it is: lies . Just because everyone does it doesn’t make it right.
Clearly we need a better measurement. I suggest picking an open core, then reporting the number that can be produced per square meter. Some choices: https://en.wikipedia.org/wiki/Category:Open_microprocessors The IBM A2 and the UltraSPARC T2 look like sane choices. Perhaps there is a suitable RISC-V. So then comparing processes, we could say that process X can do 54255 chips per square meter and process Y can do 8380…
[1] https://en.wikipedia.org/wiki/Transistor_count#Transistor_de...
Earlier quoted context omitted.
An electric signal in a wire can't travel faster than the speed of light.
> An electric signal in a wire can't travel faster than the speed of light. So? That means that the speed of light is an upper bound , but it's not a bottle neck .
If something oscillates at 1 GHz, 15 cm down the wire the phase is opposite. To me it's perfectly correct to say that speed of light affects the design a lot and in many places probably is a bottleneck.
Earlier quoted context omitted.
Why is that? What’s the point in calling it “3nm” when it’s not? Also, how is that not false advertising then? If I’m told a device is 5nm, and that traditionally meant the gate length, why isn’t it a lie when they’re actually 10nm or whatever? We need to stop calling it “marketing terms” and call it what it is: lies . Just because everyone does it doesn’t make it right.
Well because of tradition. Historically it made sense to define new technology node in terms physical gate length. But now even if that's not viable, they continue to do so for better marketing I guess.