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Clocking a 6502 simulator to 15GHz

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Re: Clocking a 6502 simulator to 15GHz

#71
post #3

I was told by Leonard Tramiel (who was my manager at Atari for a while) that the world record for a production 6502 was 25Mhz. This was demonstrated one Friday evening, some time after the beer fridge had been opened in one of the labs. I don't know if they applied any kind of external cooling, or what the benchmark was. Probably it was "keep cranking up the clock until pins stop wiggling or smoke comes out." Not ver…

One of my old companies (InformASic) developed a VPN solution for serial communication. The product LinkShield (later renamed and spun off to form CrypTango) was implemented as a small ASIC. The main CPU was a 6502 clone with memory protection. We clocked it at 33 MHz, but usually ran them at 25 MHz in the products. That 6502 clone was cycle correc, that is the number of cycles required for an instruction was the same as for the original MOS 6502.

Nowdays you can quite easily to a 6502 implementation in a FPGA running at 100 MHz. Esp if you allow the design to use more cycles for some instructions.

Sadly the product never took off and the companies folded. I have some chips somewhere. Googling at least revealed a picture of the product:

https://www.google.com/imgres?imgurl=https%3A%2F%2Ffarm3.sta...

Re: Clocking a 6502 simulator to 15GHz

#72
post #3

I was told by Leonard Tramiel (who was my manager at Atari for a while) that the world record for a production 6502 was 25Mhz. This was demonstrated one Friday evening, some time after the beer fridge had been opened in one of the labs. I don't know if they applied any kind of external cooling, or what the benchmark was. Probably it was "keep cranking up the clock until pins stop wiggling or smoke comes out." Not ver…

I love reading the stories about overclocking attempts (actually that scene doesn't seem to be much of a thing anymore?), people bolting pipes on top of CPU's and filling them with liquid nitrogen, nearly supercooling the CPU's and breaking speed records.

Re: Clocking a 6502 simulator to 15GHz

#73

Earlier quoted context omitted.

If the hardware is advanced enough to do that, the AI software is similarly advanced, and a basic 6502 can produce a Bender like AI without breaking a sweat!

More advanced software would with all likelihood require significant calculations, rendering a basic 6502 useless.

Yeah... Maybe we'd need to bump up the clock to exahertz to make up for the loss of precision and constant memory access. The top super computer is already at 148 petaflops, so we'd need some more headroom for general AI.

Of course, petaherz (10^15 cycles per second) is already the speed at which an electron circles around a hydrogen atom, so we may not be able to use electricity any more...

Re: Clocking a 6502 simulator to 15GHz

#74

Earlier quoted context omitted.

Softare expands to fill the CPU available.

AKA Wirth’s Law[1]: “Software is getting slower more rapidly than hardware is becoming faster.” [1]: https://en.m.wikipedia.org/wiki/Wirth%27s_law

Software is being produced faster though.

Re: Clocking a 6502 simulator to 15GHz

#75
post #54
post #40

Earlier quoted context omitted.

It's still surprising how little relatively to the level of perceived performance have IPC count improved since seventies.

Per TFA IPC has improved by about factor of 5, assuming a 3GHz machine runs BBC micro at equivalent performance of 15GHz

Reality for (SIMD) integer math is probably closer to 1000, floating point... probably 100000.

Re: Clocking a 6502 simulator to 15GHz

#76

It would be interesting to compare this project to simply converting 6502 assembly into LLVM IR, and letting clangs optimization passes work their magic. Obviously self modifying code would be hard to handle, but every other case ought to work, and the auto-vectorization ought to do amazing things to some loop-heavy code.

I would think you’d need to write a couple of new optimization passes, for example to detect multiplications (in various variants, such as “signed 8 bit to 16 bit, multiplier is 13” or “unsigned 16 bit times 8 bit”) and convert them to LLVM multiplication instructions.

There also is the trick where “BIT” instructions are used to give a function multiple entry points, and that BIT instruction can also be a LDA# (https://retrocomputing.stackexchange.com/a/11132)

I’m not sure that can “simply” be converted to LLVM IR.

Re: Clocking a 6502 simulator to 15GHz

#77
post #3

I was told by Leonard Tramiel (who was my manager at Atari for a while) that the world record for a production 6502 was 25Mhz. This was demonstrated one Friday evening, some time after the beer fridge had been opened in one of the labs. I don't know if they applied any kind of external cooling, or what the benchmark was. Probably it was "keep cranking up the clock until pins stop wiggling or smoke comes out." Not ver…

Can anyone with an electronics background explain why it's so hard to clock a 6502 higher than a handful of MHz, when modern chips can do 1000x that? Is it just larger transistor scale leading to excess capacitance / slower switching?

The 6502 has very limited pipelining, and every CPU cycle is tied to a memory access with no support for wait states or stalls. At 1 MHz it can work with really slow memory (roughly 500 ns), but at 10 MHz it needs ~60 ns, and at 20 MHz something like ~20ns. The architecture simply wasn't designed for anything above single digit clock speeds.

Re: Clocking a 6502 simulator to 15GHz

#79

I want to see a 6502-alike clocked to 15GHz with an exotic semiconductor such as GaAs, InP, SiGe, etc.

Probably wouldn't be able to see it with current fabrication technologies and historic transistor counts.

Exotic materials, other than maybe SiGe use fabrication techniques less advanced than Si, and the transistor counts are much less.

The department of defense funded an SBIR grant in the late 1990s to produce an InP based microprocessor, given the limits of the time it would have been closer to a 6502 than a Pentium. There has not been word of such a thing since which leads me to conclude that the topic is classified.

The worst limitation a 6502-era chip has is that it has no instruction cache so instruction reads are fighting with data for memory bandwidth. You might even consider a Harvard architecture where the instructions go on a different bus. Without an I-Cache there is no point in pipelining, but there is a lot of pressure to implement CISCy instructions such as the string copy operation from the 8086 line.

The other issue is that there is no DRAM replacement with exotic materials, and all the difficulties with interconnect latency get a lot worse than they already are. It's more clear how to make SRAM, so having somewhere between 64K to 1Mbytes of SRAM on die seems likely for an exotic material CPU.

Of course, armchair CPU designers are more likely to make progress with transition triggered architectures and FPGAs in 2020.

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