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VHDL's Crown Jewel

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Re: VHDL's Crown Jewel

#61

Post by Taniwha »

Taniwha wrote: post #17

I'm a long time verilog user (30+ years, a dozen or so tapeouts), even written a couple of compilers so I'm intimate with the gory details of event scheduling. Used to be in the early days that some people depended on how the original verilog interpreter ordered events, it was a silly thing (models would only run on one simulator, cause of lots of angst). ' In combination 'always @(*)' and '=', and assign give you re…

BTW my really big peeve about modern verilog is that it never picked up {/} as synonyms for begin/end - my experiments (20 years ago) showed that it was an easy extension, the minor syntactic ambiguities were trivally fixable

Re: VHDL's Crown Jewel

#62

Post by y1n0 »

tverbeure wrote: post #37
y1n0 wrote: post #31

Earlier quoted context omitted.

Reassigning clocks to another signal name will quickly get you into trouble in ways the just don’t happen on real hardware.

Have you heard about clock buffers and hold violations?

No, is that the latest craze?

Re: VHDL's Crown Jewel

#63

Post by seertaak »

Interesting article; I've always been fascinated and intimidated by FPGA programming - it's one of the few remaining "dark arts" of software engineering.

> VHDL’s delta cycle algorithm is its crown jewel. It gives you built-in determinism. Let us treasure it - Verilog doesn’t have anything like it. At the same time, you will agree with me that there is nothing too complicated about the concept.

I agree with you -- and thank you!

Re: VHDL's Crown Jewel

#64

Post by Joel_Mckay »

tverbeure wrote: post #46
Joel_Mckay wrote: post #27

Earlier quoted context omitted.

There are folks trying to make HDL easier, and vendor neutral. Not sure why people were upset by mentioning the project... https://github.com/amaranth-lang/amaranth While VHDL makes a fun academic toy language, it has always been Verilog in the commercial settings. Both languages can develop hard to trace bugs when the optimizer decides to simply remove things it thinks are unused. =3

> While VHDL makes a fun academic toy language, ... I spent the first half of my career working at some of the largest companies at the time on huge communication ASICs that were all written in VHDL, there was no Verilog in sight. As much as I prefer to write Verilog now, VHDL is without question a more robust and better specified language, with features that Verilog only gained a decade later through SystemVerilog.…

Note, amaranth supports both VHDL and Verilog language targets.

Cheers =3

Re: VHDL's Crown Jewel

#65

Post by artemonster »

alain94040 wrote: post #48
artemonster wrote: post #16

Please stop bickering about verilog vs vhdl - if you use NBAs the scheduler works exactly the same in modern day simulators. There is no crown jewel in vhdl anymore. Also type system is annoying. Its just in your way, not helping at all.

You're not wrong, but blocking assignments (and their equivalent in VHDL, variables), are useful as local variables to a process/always block. For instance to factor common sub-expressions and not repeat them. So using only non-blocking assignments everywhere would lead to more ugly code.

Ofc blocking assign is used too and even it that always_comb case scheduler splits eval/assign into 2 phases!
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