Hacker News Board Hacker News, browsed like a classic message board
Live data from Hacker News

Spade Hardware Description Language

spade-lang.org

Post reply on HN
Print view View original

61–64 of 64 posts

Re: Spade Hardware Description Language

#61

Post by imtringued »

grquantum wrote: post #18
Symmetry wrote: post #7

I wonder how it compares to Bluespec?

I think this commits the same sin many other new HDLs do -- it just tries to awkwardly smush the paradigm of clocked logic into a sequential software language. The abstractions just don't match, which means you lose the mental connection between the code and the generated Verilog, which makes debugging stuff like timing awkward. I'm a big Bluespec booster, and beyond the nice typing and functional programming you get…

I don't get what you're talking about. If I had to describe Spade it's just VHDL, but this time with Rust syntax instead of Pascal. The pipeline syntax is just syntax sugar and nowhere near full blown high level synthesis.

Re: Spade Hardware Description Language

#62

Post by thezoq2 »

wirybeige wrote: post #13
tails4e wrote: post #9

Earlier quoted context omitted.

SystemVerilog is a much better language than verilog. You can get pretty strong typed behaviour now, if you use the language parts that allow that. It's like C, if you use it poorly/the 'verilog way' it's got some serious footguns, but you can use it quite safely if you use the more modern features. That said, I'm all for better languages, of they really are better and as expressive

To add, even before SV we've had VHDL which is also strongly typed and has other nice features. But I do still like using SV more than VHDL :3. I'm not wholly convinced of these languages that have been popping up so far.

Spade author here :) Coming from a functional programming adjacent background, the VHDL type system leaves a lot to be desired. Not supporting types with generics means you can't encode things like a genral purpose ready/valid stream. When you have those, you can start using methods to compose those streams which becomes even more powerful when you add higher order functions which allow you to transform the content of the stream without worrying about the stream details.

Re: Spade Hardware Description Language

#63

Post by thezoq2 »

VonTum wrote: post #39

I've been wondering how long it'd take for it to show up here. I can attest to Frans (the lead dev) being a talented and highly active developer. It's frankly quite intimidating to be a competitor of his. ( https://sus.rocks ) Hopefully one day we'll break open the hardware design ecosystem. Verilog & VHDL still being de-facto industry standard is pathetic. And IMO the only reason is the white-knuckle grip Intel (Alt…

Hehe thanks for the kind words! I think once Verilog and VHDL are de-throned there will be plenty of room for more than one new HDL :) Especially if we can figure out interoperability between languages

Re: Spade Hardware Description Language

#64

Post by tails4e »

IshKebab wrote: post #49
tails4e wrote: post #9

Earlier quoted context omitted.

SystemVerilog is a much better language than verilog. You can get pretty strong typed behaviour now, if you use the language parts that allow that. It's like C, if you use it poorly/the 'verilog way' it's got some serious footguns, but you can use it quite safely if you use the more modern features. That said, I'm all for better languages, of they really are better and as expressive

It's better than Verilog but it's still awful. If you thought C had footguns....

What do you find thats so awful? Once you understand the main footguns and how to avoid them, it's overall very solid.
Post reply on HN