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Independent of instruction set, RISC-V processors will have to learn what ARM lerned. It will take time… yes
Europe bets once again on RISC-V for supercomputing
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Re: Europe bets once again on RISC-V for supercomputing
#62China recently moved that direction. That would be nice collaboration to see between EU and China. China to publish policy to boost RISC-V chip use nationwide, sources say https://www.reuters.com/technology/china-publish-policy-boos...
If the goal is to decouple from the U.S., why would the EU want to collaborate with a totalitarian state like China?
Re: Europe bets once again on RISC-V for supercomputing
#63Re: Europe bets once again on RISC-V for supercomputing
#64Earlier quoted context omitted.
Because in spite of the west's propaganda, Xi is a good dictator. Singapore was/is also a totalitarian state yet many do business with it.
Is there “good” dictatorships? My personal opinion is there is no good dictator (ok, in HN context, BDFL in a SW project) I like no totalitarian regime. No one.
I'm not just talking at the nation-state level, but at community, company, sports and so on. There's no shortage of Open Source projects run using the Benevolent Dictator approach.
Compare that to companies run by committee (or governments run by dead-locked congresses) which preport to "represent the people" but just turn into "nothing gets done" factories.
So yes, there are good dictatorships. They're especially good at getting stuff done.
There are also obviously bad dictatorships.
Re: Europe bets once again on RISC-V for supercomputing
#65I also found this report on their FPGA Emulation Platform: https://www.riser-project.eu/wp-content/uploads/2024/11/RISE...
So from these resources it seems like they develop a vector processor with Semidynamics out-of-order Atrevido core as a scalar core and their Vitruvius VPU.
There is a paper about a previous iteration of the VPU: https://dl.acm.org/doi/10.1145/3575861
In the more recent report they have a vector length of 16,384 bits, with 16 lanes (8 in FPGA, 16 in the diagram, final version could be more), so total of 16*64=1024 bits of ALUs.
Slide 15 seems to indicate that they want to create a chip with 32 of those cores, a shared L3 cache, and access to HBM.
Re: Europe bets once again on RISC-V for supercomputing
#66Re: Europe bets once again on RISC-V for supercomputing
#67Earlier quoted context omitted.
If the goal is to decouple from the U.S., why would the EU want to collaborate with a totalitarian state like China?
The US is extremely chaotic and unpredictable. China is fairly stable and predictable.
Re: Europe bets once again on RISC-V for supercomputing
#68Earlier quoted context omitted.
Both ARM and RISC-V are Reduced Instruction Set Compute (RISC) instead of Complex Instruction Set Compute (CISC aka x86) architectures. So it's more about the tooling that makes one better than the other. And like all open source, the tooling will be better over time as people and organizations recognize they get more back out of contributing to open systems.
That's way too optimistic. If it's like "all open source," it will have some improvements, forks and then nothing. There are only so many people who can contribute to chip development, and they all have jobs.
Re: Europe bets once again on RISC-V for supercomputing
#69Surely arm is a better choice?
The _current_ big EU supercomputer initiative does use ARM designs (https://www.theregister.com/2024/05/14/sipearl_rhea1_specs/ ), but you wouldn’t necessarily want to be totally dependent on them if you can help it.
Re: Europe bets once again on RISC-V for supercomputing
#70Earlier quoted context omitted.
Because in spite of the west's propaganda, Xi is a good dictator. Singapore was/is also a totalitarian state yet many do business with it.
Is there “good” dictatorships? My personal opinion is there is no good dictator (ok, in HN context, BDFL in a SW project) I like no totalitarian regime. No one.