AMD's Turin: 5th Gen EPYC Launched • Hacker News Board

Re: AMD's Turin: 5th Gen EPYC Launched

#61

Post by squarefoot » Sat, Oct 12, 2024, 9:16 AM UTC

colechristensen wrote: post #19

lukeschlather wrote: post #12

Earlier quoted context omitted.

> 16 core CPU and it rarely peaked over 30% utilization, often averaging ~25%. 30% utilization means a 6 core part (barring frequency/cache differences) should be able to eat that at 80% load. As a rule I wouldn't be surprised if 90% of the stuff Civ 6 is doing can't be parallelized at all, but then for that remaining 10% you get a 16x speedup with 16 cores. And they're underutilized on average but there are bursts w…

My rule is more like I’d be willing to bet even odds that this could be sped up 100x with the right programmers focused on performance. When you lack expertise and things work “well enough” that’s what you get. Same for games or enterprise software.

That's what we get in a market dominated more by the need to release before the competition rather than taking some time to optimize software. If it's slow, one can still blame the iron and users who don't upgrade it.

Re: AMD's Turin: 5th Gen EPYC Launched

#62

Post by menaerus » Sat, Oct 12, 2024, 9:17 AM UTC

justmarc wrote: post #52

Tuna-Fish wrote: post #49

Earlier quoted context omitted.

Great if you have 16 independent workloads, terrible for things that care about communication between threads. It has 16 CCD, each with only one thread enabled, latency between CCD is ~150ns.

Surprise surprise, not every tool is right for every job.

Not sure if this comment was about to come out as snarky but the parent rightfully pointed out the not so obvious design of EPYC CPUs. CCD is a NUMA in disguise.

Re: AMD's Turin: 5th Gen EPYC Launched

#63

Post by fecal_henge » Sat, Oct 12, 2024, 9:44 AM UTC

abenga wrote: post #45

fecal_henge wrote: post #40

Earlier quoted context omitted.

Whats wrong with an arbitary 16 digit number?

I'm sure each of the products has a numeric identifier. One can use that if they feel pressed by the "childish" names.

5318008

Re: AMD's Turin: 5th Gen EPYC Launched

#64

Post by chx » Sat, Oct 12, 2024, 9:54 AM UTC

justmarc wrote: post #50

Truly mind boggling scale. Twenty years ago we had just 1-2 cores per CPU, so we were lucky to have 4 cores in a dual socket server. A single server can now have almost 400 cores. Yes, we can have even more ARM cores but they don't perform as well as these do, at least for now.

Indeed: the first dual core server chips only launched in 2005 afaik with 90nm Denmark/Italy/Egypt Opterons and Paxville Xeons but on the Intel side it wasn't until 2007 when they were in full swing.

Re: AMD's Turin: 5th Gen EPYC Launched

#65

Post by jsheard » Sat, Oct 12, 2024, 10:02 AM UTC

p1necone wrote: post #32

mistyvales wrote: post #17

Here I am running a 12 year old Dell PowerEdge with dual Xeons.. I wonder when the first gen Epyc servers will be cheap fodder on eBay.

1-3rd gen Epycs can be had super cheap, but the motherboards are expensive. Also not worth getting anything less than 3rd gen unless you're primarily buying them for the pcie lanes and ram capacity - a regular current gen consumer CPU with half - a quarter of the core count will outperform them in compute while consuming significantly less power.

When buying used Epycs you have to contend with them possibly being vendor-locked to a specific brand of motherboard as well.

https://www.servethehome.com/amd-psb-vendor-locks-epyc-cpus-...

Re: AMD's Turin: 5th Gen EPYC Launched

#66

Post by chx » Sat, Oct 12, 2024, 10:08 AM UTC

phonon wrote: post #9

jeffbee wrote: post #6

The part with only 16 cores but 512MB L3 cache ... that must be for some specific workload.

Oracle can charge $40-$100k+ for EE including options per core (times .5)...and some workloads are very cache sensitive. So a high cache, high bandwidth, high frequency, high memory capacity 16 core CPU[1] (x2 socket) might be the best bang for their buck for that million dollar+ license. [1] https://www.amd.com/en/products/processors/server/epyc/9005-...

It is very Oracle that their license policy gives a reason to make crippled CPUs.

Re: AMD's Turin: 5th Gen EPYC Launched

#67

Post by p_l » Sat, Oct 12, 2024, 10:08 AM UTC

chx wrote: post #64

justmarc wrote: post #50

Truly mind boggling scale. Twenty years ago we had just 1-2 cores per CPU, so we were lucky to have 4 cores in a dual socket server. A single server can now have almost 400 cores. Yes, we can have even more ARM cores but they don't perform as well as these do, at least for now.

Indeed: the first dual core server chips only launched in 2005 afaik with 90nm Denmark/Italy/Egypt Opterons and Paxville Xeons but on the Intel side it wasn't until 2007 when they were in full swing.

first dual core server chips show up generally available in 2001 with IBM POWER4, then HP PA-RISC ones in 2004, and then Opterons which was followed by "emergency" design of essentially two "sockets" on one die of of NetBurst dual core systems.

Re: AMD's Turin: 5th Gen EPYC Launched

#68

Post by hales » Sat, Oct 12, 2024, 10:08 AM UTC

bpye wrote: post #13

addaon wrote: post #8

Earlier quoted context omitted.

Does anyone know if modern AMD chips allow mapping the L3 cache and using it as TCM instead of cache? I know older non-X86 processors supported this (and often booted into that mode so that the memory controllers could be brought up), but not sure if it's possible today. If so, that would sure make for some interesting embedded use cases for a large DRAM-less system...

The coreboot docs claim that modern AMD parts no longer support cache-as-RAM. https://doc.coreboot.org/soc/amd/family17h.html

Wow, thanks for the link, I had no idea:

> AMD has ported early AGESA features to the PSP, which now discovers, enables and trains DRAM. Unlike any other x86 device in coreboot, a Picasso system has DRAM online prior to the first instruction fetch.

Perhaps they saw badly trained RAM as a security flaw? Or maybe doing it with the coprocessor helped them distribute the training code more easily (I heard a rumour once that RAM training algos are heavily patented? Might have imagined it).

Re: AMD's Turin: 5th Gen EPYC Launched

#69

Post by chx » Sat, Oct 12, 2024, 10:21 AM UTC

p_l wrote: post #67

chx wrote: post #64

Earlier quoted context omitted.

Indeed: the first dual core server chips only launched in 2005 afaik with 90nm Denmark/Italy/Egypt Opterons and Paxville Xeons but on the Intel side it wasn't until 2007 when they were in full swing.

first dual core server chips show up generally available in 2001 with IBM POWER4, then HP PA-RISC ones in 2004, and then Opterons which was followed by "emergency" design of essentially two "sockets" on one die of of NetBurst dual core systems.

Ehhhh the MAJC 5200 was generally available in 1999 and I am sure even older designs could be found if we were to dig deep enough. Their market share would also need some digging too.

To quote the announcement: "two VLIW (very long instruction word) microprocessors on a single piece of silicon"

Re: AMD's Turin: 5th Gen EPYC Launched

#70

Post by formerly_proven » Sat, Oct 12, 2024, 10:43 AM UTC

chx wrote: post #69

p_l wrote: post #67

Earlier quoted context omitted.

first dual core server chips show up generally available in 2001 with IBM POWER4, then HP PA-RISC ones in 2004, and then Opterons which was followed by "emergency" design of essentially two "sockets" on one die of of NetBurst dual core systems.

Ehhhh the MAJC 5200 was generally available in 1999 and I am sure even older designs could be found if we were to dig deep enough. Their market share would also need some digging too. To quote the announcement: "two VLIW (very long instruction word) microprocessors on a single piece of silicon"

Power and PA-RISC shipped servers, though. MAJC on the other hand

> Sun built a single model of the MAJC, the two-core MAJC 5200, which was the heart of Sun's XVR-1000 and XVR-4000 workstation graphics boards.