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Intel details Skymont

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Re: Intel details Skymont

#61

Earlier quoted context omitted.

Branches that are hard to predict should be “hand-optimized” through specially written code, compiler intrinsics/annotations, or profile guided feedback to tell the compiler to emit the conditional using unconditional branchless instructions like cmov. Expecting a CPU to detect this at runtime may be asking it to do too much.

That necessitates executing both sides fully. Very often, those are "business logic" branches that are very long, and you would only prefer to cover branch mispredict penalty.

Yes you would only do this for hot loops that have short basic block branches (binary search being the canonical example). That’s why I said hand annotate vs having the CPU try to detect and distinguish these situations at runtime.

Re: Intel details Skymont

#62

Earlier quoted context omitted.

That necessitates executing both sides fully. Very often, those are "business logic" branches that are very long, and you would only prefer to cover branch mispredict penalty.

Yes you would only do this for hot loops that have short basic block branches (binary search being the canonical example). That’s why I said hand annotate vs having the CPU try to detect and distinguish these situations at runtime.

Yes, we're talking about different things. Those are able to be optimized in software doing what you mentioned. The branches I am talking about are not. They often sit in "business logic" code.

Re: Intel details Skymont

#63

Earlier quoted context omitted.

Yes you would only do this for hot loops that have short basic block branches (binary search being the canonical example). That’s why I said hand annotate vs having the CPU try to detect and distinguish these situations at runtime.

Yes, we're talking about different things. Those are able to be optimized in software doing what you mentioned. The branches I am talking about are not. They often sit in "business logic" code.

Yeah but business logic code like that isn’t generally bounded by the misprediction penalty so it doesn’t matter.

Re: Intel details Skymont

#64

How do these modern Atoms compare to the Apple ARM chips? Does Apple make something comparable in terms of power/performance?

The competitor would be the efficiency cores on the M-series chips. I don’t know how well they compare though. Apple doesn’t have any skus with only efficiency cores afaik. If they did it would be something like the Apple Watch, but since arm has had big.LITTLE architecture for many years there was no need to have chips with only efficiency cores to achieve efficiency.

Apple Watch SoCs are "just" the efficiency cores of their iPhone cousins
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