Earlier quoted context omitted.
I have a 4690K and my RAM is a 32GB EVGA DDR3 ram that I suspect was made by hynix or the other manufacturer of fast rams, that runs at speed up to par with the slowest DDR4 but with DDR3 latency, it is very awesome. I wonder if DDR5 will be fast enough to compensate for the slower latency (or maybe they improved latency this time?) To be honest I didn't felt yet any need to move off my current machine, I would only…
Latency is significantly impacted by the physical distance between RAM and CPU’s. Which combined with modern cache sizes means they get diminishing returns trying to minimize it and thus make different tradeoffs.
DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix
61–70 of 217 posts
Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix
#62Earlier quoted context omitted.
I have a 4690K and my RAM is a 32GB EVGA DDR3 ram that I suspect was made by hynix or the other manufacturer of fast rams, that runs at speed up to par with the slowest DDR4 but with DDR3 latency, it is very awesome. I wonder if DDR5 will be fast enough to compensate for the slower latency (or maybe they improved latency this time?) To be honest I didn't felt yet any need to move off my current machine, I would only…
Latency is significantly impacted by the physical distance between RAM and CPU’s. Which combined with modern cache sizes means they get diminishing returns trying to minimize it and thus make different tradeoffs.
Core-to-RAM latency is in the neighborhood of 50 ns (well-tuned Intel system with low-latency memory) to ~80 ns (bottom-of-the-barrel system). At propagation speed, that's about 10 meters. A big chunk of this latency is internal to the CPU (so is not influenced by distance to the memory at all), another big chunk is the inherent slowness of accessing a DRAM array (10+ ns, independent of the location of the memory).
It's worth pointing out how little this has changed over the past decades. A 2006 AMD CPU is 100 % competitive in regards to memory latency with Intel's 2020 flagship desktop CPU.
Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix
#63Memory piggybacked on CPUs with TSVs when?
Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix
#64I like what IBM has done with their latest power chip - effectually made the whole memory interface upgradable. https://www.nextplatform.com/2020/09/03/the-memory-area-netw... "the shift from dedicated DDR4 memory controllers to Serdes-based, high speed differential signaling mixed with buffer chips on memory modules that can be taught to speak DDR4, DDR5, GDDR6, 3D XPoint, or whatever, is an important shift in syste…
Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix
#65Earlier quoted context omitted.
Adds a latency hop, which generally can be dealt with by prefetching and larger caches on the CPU side. There's speculation that AMD is going to do the same - in Zen 2 and later designs the CPU chiplets are coupled with different IO dies depending on the design (Ryzen, Threadripper, Epyc), and swapping out the IO die for one that has support for new/different memory types would less work than taping out a whole new m…
> CPU chiplets are coupled with different IO dies depending on the design How does that differ from Intel's approach?
The AMD compute dies are only connected to the IO die and other compute dies (and power). All IO connections exclusively go through the IO die, so the IO die can be customized to change the IO of the CPU without changing anything about the compute dies. It would be entirely feasible to just re-spin the IO die to add support for different memory, Thunderbolt or other IO ports. The IO die is also made on a cheaper, lower-density and performance process (14 nm / 16 nm) than the compute dies (7 nm).
Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix
#66Earlier quoted context omitted.
Adds a latency hop, which generally can be dealt with by prefetching and larger caches on the CPU side. There's speculation that AMD is going to do the same - in Zen 2 and later designs the CPU chiplets are coupled with different IO dies depending on the design (Ryzen, Threadripper, Epyc), and swapping out the IO die for one that has support for new/different memory types would less work than taping out a whole new m…
> CPU chiplets are coupled with different IO dies depending on the design How does that differ from Intel's approach?
[1] can be overcome via caching and other considerations, but purely from this aspect the impact is this. [2] Longer traces lead to higher capacitance, and the power estimation formula P=C(V^2)f*a shows that this one aspect will change power use. Everything on one die means less parasitic capacitance. [3] If the defect density is the same, and if you have 10 errors per wafer, then you will see different yields if you make 10 vs 100 vs 1000 chips on that wafer. Chiplets are smaller than monolithic designs, so we can put more of them on one wafer which improves yield independent of process
Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix
#67Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix
#68I'm happy that I put off upgrading my pc long enough to skip a RAM generation.
Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix
#69I haven't been able to find any specs on latency, and whether it has improved or not. I assume it hasn't, because it doesn't tend to, but does anyone know for sure?