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DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

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Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#61
post #14
post #8

Earlier quoted context omitted.

I have a 4690K and my RAM is a 32GB EVGA DDR3 ram that I suspect was made by hynix or the other manufacturer of fast rams, that runs at speed up to par with the slowest DDR4 but with DDR3 latency, it is very awesome. I wonder if DDR5 will be fast enough to compensate for the slower latency (or maybe they improved latency this time?) To be honest I didn't felt yet any need to move off my current machine, I would only…

Latency is significantly impacted by the physical distance between RAM and CPU’s. Which combined with modern cache sizes means they get diminishing returns trying to minimize it and thus make different tradeoffs.

It matters but I wouldn't say it's significant for a typical design. A ns is about 12in (30cm) from Grace Hopper's famous wire visual aid.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#62
post #14
post #8

Earlier quoted context omitted.

I have a 4690K and my RAM is a 32GB EVGA DDR3 ram that I suspect was made by hynix or the other manufacturer of fast rams, that runs at speed up to par with the slowest DDR4 but with DDR3 latency, it is very awesome. I wonder if DDR5 will be fast enough to compensate for the slower latency (or maybe they improved latency this time?) To be honest I didn't felt yet any need to move off my current machine, I would only…

Latency is significantly impacted by the physical distance between RAM and CPU’s. Which combined with modern cache sizes means they get diminishing returns trying to minimize it and thus make different tradeoffs.

Is that so? I don't think it is.

Core-to-RAM latency is in the neighborhood of 50 ns (well-tuned Intel system with low-latency memory) to ~80 ns (bottom-of-the-barrel system). At propagation speed, that's about 10 meters. A big chunk of this latency is internal to the CPU (so is not influenced by distance to the memory at all), another big chunk is the inherent slowness of accessing a DRAM array (10+ ns, independent of the location of the memory).

It's worth pointing out how little this has changed over the past decades. A 2006 AMD CPU is 100 % competitive in regards to memory latency with Intel's 2020 flagship desktop CPU.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#64
post #35

I like what IBM has done with their latest power chip - effectually made the whole memory interface upgradable. https://www.nextplatform.com/2020/09/03/the-memory-area-netw... "the shift from dedicated DDR4 memory controllers to Serdes-based, high speed differential signaling mixed with buffer chips on memory modules that can be taught to speak DDR4, DDR5, GDDR6, 3D XPoint, or whatever, is an important shift in syste…

I think this makes sense for IBM, but probably not for AMD and Intel. AMD and Intel are putting out new chips every year (even if they're just Skylake refreshes), so it's not too big of a deal to change the memory interface, and they are capable of putting in two flavors of DDR support when some flexibility is needed. For IBM, I don't think they release incremental chip designs each year, so it makes more sense for them to take the tradeoff of a flexible interface, so they can get onboard with newer ram faster.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#65
post #60
post #38

Earlier quoted context omitted.

Adds a latency hop, which generally can be dealt with by prefetching and larger caches on the CPU side. There's speculation that AMD is going to do the same - in Zen 2 and later designs the CPU chiplets are coupled with different IO dies depending on the design (Ryzen, Threadripper, Epyc), and swapping out the IO die for one that has support for new/different memory types would less work than taping out a whole new m…

> CPU chiplets are coupled with different IO dies depending on the design How does that differ from Intel's approach?

Intel desktop CPUs are monolithic. A 10900K is a single die, meanwhile a AMD 3900X is three dies: two compute dies and one I/O die (which are sourced from two manufacturers on two different processes afaik). An AMD server CPU has the same compute dies, except more of them, and a very different IO die.

The AMD compute dies are only connected to the IO die and other compute dies (and power). All IO connections exclusively go through the IO die, so the IO die can be customized to change the IO of the CPU without changing anything about the compute dies. It would be entirely feasible to just re-spin the IO die to add support for different memory, Thunderbolt or other IO ports. The IO die is also made on a cheaper, lower-density and performance process (14 nm / 16 nm) than the compute dies (7 nm).

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#66
post #60
post #38

Earlier quoted context omitted.

Adds a latency hop, which generally can be dealt with by prefetching and larger caches on the CPU side. There's speculation that AMD is going to do the same - in Zen 2 and later designs the CPU chiplets are coupled with different IO dies depending on the design (Ryzen, Threadripper, Epyc), and swapping out the IO die for one that has support for new/different memory types would less work than taping out a whole new m…

> CPU chiplets are coupled with different IO dies depending on the design How does that differ from Intel's approach?

Intel uses monolithic dies, meaning everything is on the same chunk of silicon. This has given them some improvements to latency[1] and power usage[2] in the past but hurt them on yields. AMD has a chiplet design, which improves yields[3] and may allow a more modular approach as mentioned.

[1] can be overcome via caching and other considerations, but purely from this aspect the impact is this. [2] Longer traces lead to higher capacitance, and the power estimation formula P=C(V^2)f*a shows that this one aspect will change power use. Everything on one die means less parasitic capacitance. [3] If the defect density is the same, and if you have 10 errors per wafer, then you will see different yields if you make 10 vs 100 vs 1000 chips on that wafer. Chiplets are smaller than monolithic designs, so we can put more of them on one wafer which improves yield independent of process

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#67
post #52

Yeah, but to the casual user like me, that's going to help with load times... go from 2 seconds to 1 second.

Be more excited that ECC is now part of the standard, and without a speed compromise.

I guess the error rates forced them to make it part of the standard ;)

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#68

I'm happy that I put off upgrading my pc long enough to skip a RAM generation.

I try to refresh when a new ram gen launches with a new socket. That gives me a good shot at long term upgradability. Waiting on zen 4 now for my next complete build.

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#69

I haven't been able to find any specs on latency, and whether it has improved or not. I assume it hasn't, because it doesn't tend to, but does anyone know for sure?

Luckily I just posted this at AnandTech :) I couldn't find the information posted anywhere online, so I wrote it up. https://www.anandtech.com/show/16143/insights-into-ddr5-subt...

Re: DDR5 Is Coming: First 64GB DDR5-4800 Modules from SK Hynix

#70
post #28
post #20

Earlier quoted context omitted.

That reminds me, I was going to buy a PS4.

The PS5 can play PS4 games so it would be a worse financial decision I guess

Is it full automatic, pixel perfect compatibility or only a bunch of games are ?
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